Design and management of voltage-frequency island partitioned networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 3, 2009, Pages 330-341

  Ogras, Umit Y ^a,b   Marculescu, Radu ^c   Marculescu, Diana ^c   Jung, Eun Gu ^d  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

^d Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

Energy and power consumption; Multiprocessor systems on chip (MPSoCs); Networks on chip (NoCs); Voltage frequency islands (VFIs)

Indexed keywords

BIOLOGICAL MATERIALS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; ENERGY MANAGEMENT; FAULT TOLERANCE; MULTIPROCESSING SYSTEMS; QUALITY ASSURANCE; VOLTAGE CONTROL;

CLOCK-DISTRIBUTION PROBLEMS; DESIGN METHODOLOGIES; ENERGY AND POWER CONSUMPTION; ENERGY CONSUMPTION; EXCESSIVE ENERGIES; MANY CORES; MONITORING AND MANAGEMENTS; MULTIPROCESSOR SYSTEMS-ON-CHIP (MPSOCS); NETWORK-ON-CHIP ARCHITECTURES; NETWORKS-ON-CHIP (NOCS); ON THE FLIES; PARTITIONED NETWORKS; PERFORMANCE CONSTRAINTS; PROGRAMMABLE GATE ARRAYS; RUN-TIME; SIMULATION RESULTS; SYSTEM ENERGIES; VIDEO APPLICATIONS; VOLTAGE-FREQUENCY ISLANDS (VFIS);

MICROPROCESSOR CHIPS;

EID: 63149129753     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2011229     Document Type: Article

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