-
1
-
-
0034848112
-
Route Packets, Not Wires: On-Chip Interconnection Networks
-
W. J. Dally et. al. "Route Packets, Not Wires: On-Chip Interconnection Networks," in the Proc. of DAC, pp. 684-689, 2001.
-
(2001)
Proc. of DAC
, pp. 684-689
-
-
Dally, W.J.1
et., al.2
-
2
-
-
85165855460
-
-
http://helsinki.ee.Princeton.EDU/ dickrp/tgff
-
-
-
-
5
-
-
85165865349
-
-
Kim, N. et al., Visual Assessment of a Real-time System Design: A Case Study on a CNC Controller, RTSS, 1996.
-
Kim, N. et al., "Visual Assessment of a Real-time System Design: A Case Study on a CNC Controller," RTSS, 1996.
-
-
-
-
6
-
-
85165856566
-
-
T. Dumitras and R. Marculescu, On-chip stochastic communication, In DATE, pp. 790-795, 2003.
-
T. Dumitras and R. Marculescu, "On-chip stochastic communication," In DATE, pp. 790-795, 2003.
-
-
-
-
7
-
-
16244415711
-
Bandwidth-constrained mapping of cores onto NoC architectures
-
Feb
-
S. Murali and G. De Micheli, "Bandwidth-constrained mapping of cores onto NoC architectures," in Proc. DATE, pp. 16-20, Feb. 2004.
-
(2004)
Proc. DATE
, pp. 16-20
-
-
Murali, S.1
De Micheli, G.2
-
8
-
-
16244389647
-
Application-Specific Buffer Space allocation for Networks-on-Chip Router Design
-
J. Hu, R. Marculescu, "Application-Specific Buffer Space allocation for Networks-on-Chip Router Design," in the Proc. of ICCAD, pp. 354-361, 2004
-
(2004)
Proc. of ICCAD
, pp. 354-361
-
-
Hu, J.1
Marculescu, R.2
-
9
-
-
0003937287
-
Interconnection Networks, an Engineering Approach
-
J. Duato, S. Yalamanchili, L. Ni, Interconnection Networks, an Engineering Approach, IEEE Computer Society Press, 1997.
-
(1997)
IEEE Computer Society Press
-
-
Duato, J.1
Yalamanchili, S.2
Ni, L.3
-
10
-
-
84861905550
-
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
-
Cesar Marcon et al., "Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique," in the Proc. of DATE, pp. 502-507, 2005.
-
(2005)
Proc. of DATE
, pp. 502-507
-
-
Marcon, C.1
-
11
-
-
28444450874
-
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
-
Tobias Bjerregaard and Jens Sparsø,"A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip," in the Proc. of ASYNC, pp. 34-43, 2005.
-
(2005)
Proc. of ASYNC
, pp. 34-43
-
-
Bjerregaard, T.1
Sparsø, J.2
-
12
-
-
84893687806
-
A generic architecture for on-chip packet-switched interconnections
-
P. Guerrier and A. Greiner, "A generic architecture for on-chip packet-switched interconnections," in the Proc. of DATE, pp. 250-256, 2000.
-
(2000)
Proc. of DATE
, pp. 250-256
-
-
Guerrier, P.1
Greiner, A.2
-
13
-
-
85165845548
-
-
E. Rijpkema et.la., Trades-offs in the design of a router with both guaranteed and best-effort services for networks on chip, in the Proc. On Comput. Digit. Tech. 150, Issue 5, pp. 294-302, Sept. 2003
-
E. Rijpkema et.la., "Trades-offs in the design of a router with both guaranteed and best-effort services for networks on chip," in the Proc. On Comput. Digit. Tech. Vol. 150, Issue 5, pp. 294-302, Sept. 2003
-
-
-
-
14
-
-
0027579765
-
Deadlock -free adaptive routing in multicomputer networks using virtual channels
-
April
-
W.J. Dally, H. Aoki, "Deadlock -free adaptive routing in multicomputer networks using virtual channels," IEEE Transactions on Parallel and Distributed Systems pp. 466-475, April, 1993
-
(1993)
IEEE Transactions on Parallel and Distributed Systems
, pp. 466-475
-
-
Dally, W.J.1
Aoki, H.2
-
15
-
-
85165850994
-
-
V. S. Adve and M. K. Vernon, Performance analysis of mesh interconnection networks with deterministic routing, IEEE Tran. on Parallel and Distributed Systems, pp.225.246, March 1994.
-
V. S. Adve and M. K. Vernon, "Performance analysis of mesh interconnection networks with deterministic routing," IEEE Tran. on Parallel and Distributed Systems, pp.225.246, March 1994.
-
-
-
|