Globally-synchronized frames for guaranteed quality-of-service in on-chip networks

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2008, Pages 89-100

  Lee, Jae W ^a   Ng, Man Cheuk ^a   Asanović, Krste ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE THROUGHPUT; BAND-WIDTH ALLOCATION; BEST EFFORTS; CHIP MULTI PROCESSORS; GUARANTEED QUALITY; HARDWARE COMPLEXITIES; INTERNATIONAL SYMPOSIUM; MAXIMUM DELAY BOUND; MEMORY CONTROLLERS; MESH NETWORKS; MULTI HOPPING; ON CHIPS; ON-CHIP NETWORKS; PERFORMANCE GUARANTEES; QOS SUPPORTS; SHARED RESOURCES; SYSTEM UTILIZATION; VIRTUAL CHANNELS;

BANDWIDTH; CHLORINE COMPOUNDS; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; COMPUTER SYSTEMS; COMPUTERS; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; MESH GENERATION; ROUTERS; SULFATE MINERALS; TELECOMMUNICATION NETWORKS; TELECOMMUNICATION SYSTEMS; VIRTUAL REALITY;

QUALITY OF SERVICE;

EID: 52649094492     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2008.31     Document Type: Conference Paper

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