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Volumn , Issue , 2004, Pages 182-187

Multi-objective mapping for mesh-based NoC architectures

Author keywords

Genetic algorithms; Mapping; Multi objective optimization; Network on chip; Simulation

Indexed keywords

COMPUTER SIMULATION; DECODING; ENCODING (SYMBOLS); EVOLUTIONARY ALGORITHMS; GENETIC ALGORITHMS; MICROPROCESSOR CHIPS; OPTIMIZATION; STANDARDS; TELECOMMUNICATION TRAFFIC;

EID: 16244409520     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016720.1016765     Document Type: Conference Paper
Times cited : (199)

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    • Banerjee, N.1    Vellanki, P.2    Chatha, K.S.3
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    • Dally, W.J.1    Towles, B.2
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    • Energy-aware mapping for tile-based NoC architectures under performance constraints
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    • J. Hu and R. Marculescu. Energy-aware mapping for tile-based NoC architectures under performance constraints. In Asia & South Pacific Design Automation Conference, Jan. 2003.
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    • Hu, J.1    Marculescu, R.2
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    • A two-step genetic algorithm for mapping task graphs to a network on chip architecture
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    • T. Lei and S. Kumar. A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In Euromicro Symposium on Digital Systems Design, Sept. 1-6 2003.
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    • Lei, T.1    Kumar, S.2
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    • Bandwidth-constrained mapping of cores onto NoC architectures
    • IEEE Computer Society, Feb. 16-20
    • S. Murali and G. D. Micheli. Bandwidth-constrained mapping of cores onto NoC architectures. In Design, Automation, and Test in Europe, pages 896-901. IEEE Computer Society, Feb. 16-20 2004.
    • (2004) Design, Automation, and Test in Europe , pp. 896-901
    • Murali, S.1    Micheli, G.D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.