Design of resonant global clock distributions

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 248-253

  Chan, Steven C ^a   Shepard, Kenneth L ^a   Restle, Phillip J ^b  

^a Department of Earth and Environmental Sciences   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT RESONANCE; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; FREQUENCY DOMAIN ANALYSIS; INTEGRATED CIRCUIT LAYOUT; NATURAL FREQUENCIES; TIME DOMAIN ANALYSIS; TIMING JITTER;

CLOCK LATENCY; GLOBAL CLOCK DISTRIBUTION; ON-CHIP INDUCTORS; SOFTWARE PACKAGE SPECTRE;

TIMING CIRCUITS;

EID: 0344982108     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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