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Volumn 2005, Issue , 2005, Pages 456-460

Compiler-directed voltage scaling on communication links for reducing power consumption

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; ELECTRIC POTENTIAL; IMAGE PROCESSING; LARGE SCALE SYSTEMS; MULTIMEDIA SYSTEMS; OPTIMIZATION; TELECOMMUNICATION LINKS; TELECOMMUNICATION NETWORKS; TOPOLOGY;

EID: 33751432061     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560111     Document Type: Conference Paper
Times cited : (14)

References (21)
  • 1
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    • A. Agarwal, "Limits on interconnection network performance," IEEE Trans. on Parallel and Distr. Systems, vol. 2, no. 4, Oct. 1991.
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    • Agarwal, A.1
  • 2
    • 0025448089 scopus 로고
    • Performance analysis of k-ary n-cube interconnection networks
    • June
    • W. J. Dally, "Performance analysis of k-ary n-cube interconnection networks," IEEE Trans. on Computers, vol. 39, no. 6, June 1990.
    • (1990) IEEE Trans. on Computers , vol.39 , Issue.6
    • Dally, W.J.1
  • 4
    • 0023367346 scopus 로고
    • The performance of multicomputer interconnection networks
    • June
    • D. A. Reed and D. C. Grunwald, "The performance of multicomputer interconnection networks," IEEE Transaction on Computers, vol. 20, no. 6, June 1987.
    • (1987) IEEE Transaction on Computers , vol.20 , Issue.6
    • Reed, D.A.1    Grunwald, D.C.2
  • 5
    • 0034785285 scopus 로고    scopus 로고
    • Powering networks on chips: Energy-efficient and reliable interconnect design for SoCs
    • L. Benini and G. D. Micheli, "Powering networks on chips: energy-efficient and reliable interconnect design for SoCs," in Proc. the 14th Int. Symp. on Systems Synthesis, 2001.
    • (2001) Proc. the 14th Int. Symp. on Systems Synthesis
    • Benini, L.1    Micheli, G.D.2
  • 8
    • 84955452760 scopus 로고    scopus 로고
    • Dynamic voltage scaling with links for power optimization of interconnection networks
    • Feb.
    • L. Shang, L.-S. Peh, and N. K. Jha, "Dynamic voltage scaling with links for power optimization of interconnection networks," in Proc. HPCA, Feb. 2003.
    • (2003) Proc. HPCA
    • Shang, L.1    Peh, L.-S.2    Jha, N.K.3
  • 9
    • 1542326696 scopus 로고    scopus 로고
    • Adaptive supply serial links with sub-IV operation and per-pin clock recovery
    • Feb.
    • J. Kim and M. Horowitz, "Adaptive supply serial links with sub-IV operation and per-pin clock recovery," in Proc. Int. Solid-State Circuits Conf., Feb. 2002.
    • (2002) Proc. Int. Solid-state Circuits Conf.
    • Kim, J.1    Horowitz, M.2
  • 15
    • 0031373275 scopus 로고    scopus 로고
    • Power constrained design of multiprocessor interconnection networks
    • Washington, DC, USA
    • C. S. Patel, "Power constrained design of multiprocessor interconnection networks," in Proc. the Int. Conf. on Computer Design, Washington, DC, USA, 1997.
    • (1997) Proc. the Int. Conf. on Computer Design
    • Patel, C.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.