"It's a small world after all": NoC performance optimization via long-range link insertion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 7, 2006, Pages 693-706

  Ogras, Umit Y ^a,b   Marculescu, Radu ^a,b  

^a IEEE   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Design automation; Multiprocessor system on chip (MP SoC); Network on chip (NoC); Performance analysis

Indexed keywords

COMMUNICATION ARCHITECTURE; DESIGN AUTOMATION; MULTIPROCESSOR SYSTEM-ON-CHIP (MP-SOC); NETWORK-ON-CHIP (NOC); PERFORMANCE ANALYSIS;

CHIP SCALE PACKAGES; COMMUNICATION SYSTEMS; COMPUTER ARCHITECTURE; CONGESTION CONTROL (COMMUNICATION); TELECOMMUNICATION TRAFFIC; TOPOLOGY;

INTERCONNECTION NETWORKS;

EID: 33746930901     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.878263     Document Type: Conference Paper

References (44)

1. A. Adriahantenaina and A. Greiner, "Micro-network for SoC: implementation of a 32-Port SPIN network," in Proc. DATE, 2003, pp. 1128-1129.
2. G. Ascia, V. Catania, and M. Palesi, "Multi-objective mapping for mesh-based NoC architectures," in Proc. ISSS-CODES, 2004, pp. 182-187.
3. T. A. Bartic et al., "Highly scalable network on chip for reconfigurable systems," in Proc. Int. Symp. System-on-Chip, 2003, pp. 79-82.
4. L. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm," IEEE Comput., vol. 35, no. 1, pp. 70-78, Jan. 2002.
5. D. Bertozzi et al., "NoC synthesis flow for customized domain specific multiprocessor systems-on-chip," IEEE Trans. Parallel Distrib. Syst., vol. 16, no. 2, pp. 113-129, Feb. 2005.
6. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "QNoC: QoS architecture and design process for network on chip," J. Syst. Architecture: EUROMICRO J., vol. 50, pp. 105-128, Feb. 2004.
7. L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli, "Theory of latency-insensitive design," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 9, pp. 1059-1076, Sep. 2001.
8. V. Chandra, A. Xu, H. Schmit, and L. Pileggi, "An interconnect channel design methodology for high performance integrated circuits," in Proc. DATE, 2004, pp. 1138-1143.
9. G. Chiu, "The odd-even turn model for adaptive routing," IEEE Trans. Parallel Distrib. Syst., vol. 11, no. 7, pp. 729-738, Jul. 2000.
10. W. J. Dally, "Express cubes: improving the performance of k-ary n-cube interconnection networks," IEEE Trans. Comput., vol. 40, no. 9, pp. 1016-1023, Sep. 1991.
11. W. J. Dally and C. L. Seitz, "Deadlock-free message routing in multi-processor interconnection networks," IEEE Trans. Comput., vol. C-36, no. 5, pp. 547-553, May 1987.
12. W. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. DAC, 2001, pp. 684-689.
13. R. Dick, Embedded System Synthesis Benchmarks Suites (E3S) [On-line]. Available: http://www.ece.northwestern.edu/~dickrp/e3s/
14. J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks: An Engineering Approach. San Mateo, CA: Morgan Kaufmann, 2002.
15. H. Fuks and A. Lawniczak, "Performance of data networks with random links," Math. Comput. Simulation, vol. 51, pp. 101-117, Dec. 1999.
16. C. J. Glass and L. M. Ni, "The turn model for adaptive routing," in Proc. ISCA, 1992, pp. 278-287.
17. K. Goossens et al., "A design flow for application-specific networks-on-chip with guaranteed performance to accelerate SoC design and verification," in Proc. DATE, 2005, pp. 1182-1187.
18. A. Hemani et al., "Network on a chip: An architecture for billion transistor era," in Proc. IEEE NorChip Conf., 2000, pp. 166-173.
19. J. Hu and R. Marculescu, "Energy- and performance-aware mapping for regular NoC architectures," IEEE Trans. Comput. -Aided Design Integr. Circuits Syst., vol. 24, no. 4, pp. 551-562, Apr. 2005.
20. _, "Application-specific buffer space allocation for networks-on-chip router design," in Proc. ICCAD, 2004, pp. 354-361.
21. A. Jantsch and H. Tenhunen, Eds., Networks-on-Chip. Norwell, MA: Kluwer, 2003.
22. J. Kleinberg, "Navigation in a small world," Nature, vol. 406, p. 845, 2000.
23. H. G. Lee, K. Lee, Y. Choi, and N. Chang, "Cycle-accurate energy measurement and characterization of FPGAs," Analog Integr. Circuits Signal Process., vol. 42, pp. 239-251, 2005.
24. J. Liang, A. Laffely, S. Srinivasan, and R. Tessier, "An architecture and compiler for scalable on-chip communication," IEEE Trans. VLSI Syst., vol. 12, no. 7, pp. 711-726, 2004.
25. S. Loucif, M. Ould-Khaoua, and L. M. Mackenzie, "On the performance merits of bypass channels in hypermeshes and k-ary n-cubes," Comput. J., vol. 42, no. 1, pp. 62-72, 1999.
26. M. Millberg, E. Nilsson, R. Thid, S. Kumar, and A. Jantsch, "The Nostrum backbone - a communication protocol stack for networks on chip," in Proc. VLSI Design, 2004, pp. 693-696.
27. S. Murali and G. De Micheli, "Bandwidth-constrained mapping of cores onto NoC architectures," in Proc. DATE, Mar. 2004, pp. 896-903.
28. _, "SUNMAP: A tool for automatic topology selection and generation for NoCs," in Proc. DAC, 2004, pp. 914-919.
29. S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli, "Mapping and configuration methods for multi-use-case networks on chips," in Proc. ASP-DAC, 2006, pp. 146-151.
30. M. E. J. Newman and D. J. Watts, "Scaling and percolation in the small-world network model," Phys. Rev. E, vol. 60, pp. 7332-7342, 1999.
31. M. Newman, "The structure and function of complex networks," SIAM Rev., vol. 45, no. 2, pp. 167-256, 2003.
32. U. Y. Ogras and R. Marculescu, "Energy- and performance-driven customized architecture synthesis using a decomposition approach," in Proc. DATE, 2005, pp. 352-357.
33. U. Y. Ogras, R. Marculescu, H. G. Lee, and N. Chang, "Communication architecture optimization: Making the shortest path shorter in regular networks-on-chip," in Proc. DATE, 2006, pp. 712-717.
34. T. Ohira and R. Sawatari, "Phase transition in computer network traffic," Phys. Rev. E, vol. 58, pp. 193-195, 1998.
35. A. Pinto, L. P. Carloni, and A. L. Sangiovanni-Vincentelli, "Efficient synthesis of networks on chip," in Proc. ICCD, 2003, pp. 146-150.
36. M. Sgroi et al., "Addressing the system-on-a-chip interconnect woes through communication-based design," in Proc. DAC, 2001, pp. 667-672.
37. T. Simunic, L. Benini, A. Acquaviva, P. Glynn, and G. D. Micheli, "Dynamic voltage scaling and power management for portable systems," in Proc. DAC, 2001, pp. 524-529.
38. K. Srinivasan, K. S. Chatha, and G. Konjevod, "Linear programming based techniques for synthesis of network-on-chip architectures," in Proc. ICCD, 2004, pp. 422-429.
39. H. Wang, L. Peh, and S. Malik, "A technology-aware and energy-oriented topology exploration for on-chip networks," in Proc. DATE, 2005, pp. 1238-1243.
40. H. Wang, X. Zhu, L. Peh, and S. Malik, "Orion: A power-performance simulator for interconnection networks," in Proc. MICRO, 2002, pp. 294-305.
41. D. J. Watts, Small Worlds, The Dynamics of Networks Between Order and Randomness. Princeton, NJ: Princeton Univ. Press, 1999.
42. D. J. Watts and S. H. Strogatz, "Collective dynamics of 'small-world' networks," Nature, vol. 393, pp. 440-442, 1998.
43. M. Woolf, D. K. Arrowsmith, R. J. Mondragon-C, and J. M. Pitts, "Optimization and phase transitions in a chaotic model of data traffic," Phys. Rev. E, vol. 66, no. 2002, p. 046106.
44. T. T. Ye, L. Benini, and G. De Micheli, "Analysis of power consumption on switch fabrics in network routers," in Proc. DAC, 2002, pp. 524-529.