Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2001, Pages 118-126

  Bainbridge, W J ^a   Furber, S B ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUIT INTERCONNECTS; MULTIPLEXING EQUIPMENT; PROGRAMMABLE LOGIC CONTROLLERS; SIGNAL ENCODING; SYSTEM-ON-CHIP;

AREA REQUIREMENT; DATA ENCODING; HIGH-THROUGHPUT; LONGEST PATH; POINT-TO-POINT CONNECTIONS; SHARED BUS; SIMPLE++; SYSTEM-ON-CHIP BUS; SYSTEM-ON-CHIP INTERCONNECTS; TRISTATE;

BUSES;

EID: 77957933800     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2001.914075     Document Type: Conference Paper

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