Synthesis of synchronous elastic architectures

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 657-662

  Cortadella, Jordi ^a   Kishinevsky, Mike ^b   Grundmann, Bill ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b INTEL CORPORATION   (United States)

Author keywords

Latency insensitive design; Latency tolerance; Protocols; Synthesis

Indexed keywords

ARCHITECTURAL DESIGN; COMMUNICATION CHANNELS (INFORMATION THEORY); ELASTICITY; SPECIFICATIONS;

LATENCY TOLERANCE; LATENCY-INSENSITIVE DESIGN; MICROARCHITECTURAL DESIGN; SYNCHRONOUS ELASTIC ARCHITECTURES;

ELECTRIC NETWORK ANALYSIS;

EID: 34547185654     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147077     Document Type: Conference Paper

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