Analysis of power consumption on switch fabrics in network routers

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 524-529

  Ye, Terry Tao ^a   Benini, Luca ^a   De Micheli, Giovanni ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Interconnect Networks; Networks on Chip; Power Consumption; Systems on Chip

Indexed keywords

BUFFER CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; INTERCONNECTION NETWORKS; SWITCHES;

BIT-LEVEL ACCURACY; POWER CONSUMPTION; SWITCH FABRICS;

ROUTERS;

EID: 0036053347     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2002.1012681     Document Type: Conference Paper

References (11)

1. Broadband Packet Switching Technologies: A Practical Guide to ATM Switches and IP Routers
2. Low-power system-level design of VLSI packet switching fabrics
3. Power constrained design of multiprocessor interconnection networks
4. High level estimation of the area and power consumption of on-chip interconnects
5. The future of wigs
6. Compact, multilayer layout for butterfly fat-free
7. Memory system energy: Influence of hardware-software optimizations
8. Memory exploration for low power, embedded systems
9. Structure and performance evaluation of a replicated banyan network based ATM switch
10. Design and performance evaluation of a banyan network based interconnection structure for ATM switches