-
2
-
-
0024103902
-
Radiation effects on microelectronics in space
-
Nov.
-
J. R. Srour and J. M. McGarrity, "Radiation effects on microelectronics in space," Proc. IEEE, vol. 76, no. 11, pp. 1443-1469, Nov. 1988.
-
(1988)
Proc. IEEE
, vol.76
, Issue.11
, pp. 1443-1469
-
-
Srour, J.R.1
McGarrity, J.M.2
-
3
-
-
0033362679
-
Technology and design challenges for low power and high performance
-
V. De and S. Borkar, "Technology and design challenges for low power and high performance," in Proc. Int. Symp. Low-Power Electron. Des., 1999, pp. 163-168.
-
(1999)
Proc. Int. Symp. Low-power Electron. Des.
, pp. 163-168
-
-
De, V.1
Borkar, S.2
-
4
-
-
0242659354
-
Selective node engineering for chip-level soft error rate improvement
-
T. Karnik and S. Vangal, "Selective node engineering for chip-level soft error rate improvement," in Proc. Symp. VLSI Circuits. 2002, pp. 132-135.
-
(2002)
Proc. Symp. VLSI Circuits
, pp. 132-135
-
-
Karnik, T.1
Vangal, S.2
-
5
-
-
0034450511
-
Impact of CMOS technology scaling on the atmospheric neutron soft error rate
-
Dec.
-
P. Hazucha and C. Svensson, "Impact of CMOS technology scaling on the atmospheric neutron soft error rate," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2586-2594, Dec. 2000.
-
(2000)
IEEE Trans. Nucl. Sci.
, vol.47
, Issue.6
, pp. 2586-2594
-
-
Hazucha, P.1
Svensson, C.2
-
6
-
-
1542690244
-
Soft errors in advanced semiconductor devices-Part I: The three radiation sources
-
Mar.
-
R. C. Baumann, "Soft errors in advanced semiconductor devices-Part I: The three radiation sources," IEEE Trans. Device Mater. Reliab., vol. 1, no. 1, pp. 17-22, Mar. 2001.
-
(2001)
IEEE Trans. Device Mater. Reliab.
, vol.1
, Issue.1
, pp. 17-22
-
-
Baumann, R.C.1
-
7
-
-
0033667091
-
Reliable low-power design in the presence of deep submicron noise
-
N. R. Shanbhag, K. Soumyanath, and S. Martin, "Reliable low-power design in the presence of deep submicron noise," in Proc. Int. Symp. Low-Power Electron. Des., 2000, pp. 295-302.
-
(2000)
Proc. Int. Symp. Low-power Electron. Des.
, pp. 295-302
-
-
Shanbhag, N.R.1
Soumyanath, K.2
Martin, S.3
-
8
-
-
1842582494
-
Reliable and efficient system-on-chip design
-
Mar.
-
N. R. Shanbhag, "Reliable and efficient system-on-chip design," IEEE Computer, vol. 37, no. 3, pp. 42-50, Mar. 2004.
-
(2004)
IEEE Computer
, vol.37
, Issue.3
, pp. 42-50
-
-
Shanbhag, N.R.1
-
9
-
-
84962745359
-
Concurrent detection of soft errors based on current monitoring
-
Y. Tsiatouhas, T. Haniotakis, D. Nikolos, and C. Efstathiou, "Concurrent detection of soft errors based on current monitoring," in On-line Testing Workshop, 2001, pp. 106-110.
-
(2001)
On-line Testing Workshop
, pp. 106-110
-
-
Tsiatouhas, Y.1
Haniotakis, T.2
Nikolos, D.3
Efstathiou, C.4
-
10
-
-
0032226711
-
Methods for reducing soft errors in deep submicron integrated circuits
-
K. Zhang, S. Hareland, B. Senyk, and J. Maiz, "Methods for reducing soft errors in deep submicron integrated circuits," in Proc. Solid-State Integr. Circuit Technol., 1998, pp. 516-519.
-
(1998)
Proc. Solid-state Integr. Circuit Technol.
, pp. 516-519
-
-
Zhang, K.1
Hareland, S.2
Senyk, B.3
Maiz, J.4
-
12
-
-
0034452351
-
Analysis of single-event effects in combinational logic-Simulation of the AM2901 bitslice processor
-
Dec.
-
L. W. Massengill, A. E. Baranski, D. Nort, J. Meng, and B. L. Bhuva, "Analysis of single-event effects in combinational logic-Simulation of the AM2901 bitslice processor," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2609-2615, Dec. 2000.
-
(2000)
IEEE Trans. Nucl. Sci.
, vol.47
, Issue.6
, pp. 2609-2615
-
-
Massengill, L.W.1
Baranski, A.E.2
Nort, D.3
Meng, J.4
Bhuva, B.L.5
-
13
-
-
0036045251
-
Managing soft errors in ASICs
-
L. Wissel, S. Pheasant, R. Loughran, and C. LeBlanc, "Managing soft errors in ASICs," in Proc. Custom Integr. Circuits Conf., 2002, pp. 85-88.
-
(2002)
Proc. Custom Integr. Circuits Conf.
, pp. 85-88
-
-
Wissel, L.1
Pheasant, S.2
Loughran, R.3
LeBlanc, C.4
-
14
-
-
0036931372
-
Modeling the effect of technology trend on the soft error rate of combinational logic
-
P. Shivakumar, "Modeling the effect of technology trend on the soft error rate of combinational logic," in Proc. Int. Conf. Dependable Syst. Netw., 2002, pp. 389-398.
-
(2002)
Proc. Int. Conf. Dependable Syst. Netw.
, pp. 389-398
-
-
Shivakumar, P.1
-
16
-
-
0036927879
-
The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction
-
R. Baumann, "The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction," in Dig. Int. Electron Devices Meeting, 2002, pp. 329-332.
-
(2002)
Dig. Int. Electron Devices Meeting
, pp. 329-332
-
-
Baumann, R.1
-
17
-
-
0035789646
-
REESE: A method of soft error detection in microprocessors
-
J. B. Nickel and A. K. Somani, "REESE: A method of soft error detection in microprocessors," Dependable Syst. Netw., pp. 401-410, 2001.
-
(2001)
Dependable Syst. Netw.
, pp. 401-410
-
-
Nickel, J.B.1
Somani, A.K.2
-
18
-
-
0027646699
-
Exploiting redundancy to speed up parallel systems
-
I. Yen, E. L. Leiss, and F. B. Bastani, "Exploiting redundancy to speed up parallel systems," in Proc. Parallel Distributed Tech., 1993, pp. 51-60.
-
(1993)
Proc. Parallel Distributed Tech.
, pp. 51-60
-
-
Yen, I.1
Leiss, E.L.2
Bastani, F.B.3
-
19
-
-
0033750857
-
Self-checking circuits versus realistic faults in very deep submicron
-
L. Anghel, M. Nicolaidis, and M. Alzaher-Noufal, "Self-checking circuits versus realistic faults in very deep submicron," Proc. IEEE VLSI Test Symp., pp. 55-63, 2000.
-
(2000)
Proc. IEEE VLSI Test Symp.
, pp. 55-63
-
-
Anghel, L.1
Nicolaidis, M.2
Alzaher-Noufal, M.3
-
20
-
-
84944215733
-
Evaluation of a soft error tolerance technique based on time and/or space redundancy
-
L. Anghel, D. Alexandrescu, and M. Nicolaidis, "Evaluation of a soft error tolerance technique based on time and/or space redundancy," Integr. Circuits Syst. Des., pp. 237-242, 2000.
-
(2000)
Integr. Circuits Syst. Des.
, pp. 237-242
-
-
Anghel, L.1
Alexandrescu, D.2
Nicolaidis, M.3
-
21
-
-
0026953435
-
An on-chip ECC for correcting soft errors in DRAM's with trench capacitors
-
Nov.
-
P. Mazumder, "An on-chip ECC for correcting soft errors in DRAM's with trench capacitors," IEEE J. Solid-State Circuits., vol. 27, no. 11, pp. 1623-1633, Nov. 1992.
-
(1992)
IEEE J. Solid-state Circuits
, vol.27
, Issue.11
, pp. 1623-1633
-
-
Mazumder, P.1
-
22
-
-
0033321638
-
DIVA: A reliable substrate for deep submicron microarchitecture design
-
T. Austin, "DIVA: A reliable substrate for deep submicron microarchitecture design," in Proc. Int. Symp. Microarch., 1999, pp. 196-207.
-
(1999)
Proc. Int. Symp. Microarch.
, pp. 196-207
-
-
Austin, T.1
-
23
-
-
0035706021
-
Soft digital signal processing
-
Dec.
-
R. Hegde and N. R. Shanbhag, "Soft digital signal processing," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 6, pp. 813-823, Dec. 2001.
-
(2001)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.9
, Issue.6
, pp. 813-823
-
-
Hegde, R.1
Shanbhag, N.R.2
-
24
-
-
0037306141
-
Low-power filtering via adaptive errorcancellation
-
Feb.
-
L. Wang and N. R. Shanbhag, "Low-power filtering via adaptive errorcancellation," IEEE Trans. Signal Process., vol. 51, no. 2, pp. 575-583, Feb. 2003.
-
(2003)
IEEE Trans. Signal Process.
, vol.51
, Issue.2
, pp. 575-583
-
-
Wang, L.1
Shanbhag, N.R.2
-
25
-
-
2542436055
-
Low-power digital signal processing via reduced precision redundancy
-
May
-
B. Shim, S. Sridhara, and N. R. Shanbhag, "Low-Power digital signal processing via reduced precision redundancy," IEEE Trans. Very Large Scale Integr. Syst., vol. 12, no. 5, pp. 497-510, May 2004.
-
(2004)
IEEE Trans. Very Large Scale Integr. Syst.
, vol.12
, Issue.5
, pp. 497-510
-
-
Shim, B.1
Sridhara, S.2
Shanbhag, N.R.3
-
26
-
-
17044382607
-
A novel forward-backward predictor based low-power DSP system
-
B. Shim, M. Zhang, and N. Shanbhag, "A novel forward-backward predictor based low-power DSP system," in Proc. IEEE Workshop Signal Process. Syst. Implementation (SiPS), 2004, pp. 331-336.
-
(2004)
Proc. IEEE Workshop Signal Process. Syst. Implementation (SiPS)
, pp. 331-336
-
-
Shim, B.1
Zhang, M.2
Shanbhag, N.3
-
28
-
-
0028516986
-
A time redundancy approach to TMR failures using fault-state likelihoods
-
Oct.
-
K. G. Shin and H. Kim, "A time redundancy approach to TMR failures using fault-state likelihoods," IEEE Trans. Computers, vol. 43, no. 10, pp. 1151-1162, Oct. 1994.
-
(1994)
IEEE Trans. Computers
, vol.43
, Issue.10
, pp. 1151-1162
-
-
Shin, K.G.1
Kim, H.2
-
29
-
-
1242263405
-
A voltage overscaled low-power digital filter IC
-
Feb.
-
R. Hegde and N. R. Shanbhag, "A voltage overscaled low-power digital filter IC," IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 388-391, Feb. 2004.
-
(2004)
IEEE J. Solid-state Circuits
, vol.39
, Issue.2
, pp. 388-391
-
-
Hegde, R.1
Shanbhag, N.R.2
-
33
-
-
0030375853
-
Upset hardened memory design for submicron CMOS technology
-
Dec.
-
T. Calin, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2874-2878, Dec. 1996.
-
(1996)
IEEE Trans. Nucl. Sci.
, vol.43
, Issue.6
, pp. 2874-2878
-
-
Calin, T.1
|