-
1
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
L. Benini G. De Micheli Networks on chips: a new SoC paradigm. IEEE Computer 35 2002 1 70 78
-
(2002)
IEEE Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
De Micheli, G.2
-
4
-
-
27344448207
-
A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification
-
Munich, Germany
-
K. Goossens J. Dielissen O. P. Gangwal S. G. Pestana A. Rdulescu E. Rijpkema A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '05) 2 Munich, Germany 2005 1182 1187
-
(2005)
Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '05)
, vol.2
, pp. 1182-1187
-
-
Goossens, K.1
Dielissen, J.2
Gangwal, O.P.3
Pestana, S.G.4
Rdulescu, A.5
Rijpkema, E.6
-
9
-
-
34047170421
-
Contrasting a NoC and a traditional interconnect fabric with layout awareness
-
Munich, Germany
-
F. Angiolini P. Meloni S. Carta L. Benini L. Raffo Contrasting a NoC and a traditional interconnect fabric with layout awareness. Proceedings of Design, Automation and Test in Europe (DATE '06) 1 Munich, Germany 2006 124 129
-
(2006)
Proceedings of Design, Automation and Test in Europe (DATE '06)
, vol.1
, pp. 124-129
-
-
Angiolini, F.1
Meloni, P.2
Carta, S.3
Benini, L.4
Raffo, L.5
-
15
-
-
4444335188
-
SUNMAP: A tool for automatic topology selection and generation for NoCs
-
smurali@stanford.edu nanni@stanford.edu San Diego, Calif, USA
-
S. Murali smurali@stanford.edu G. De Micheli nanni@stanford.edu SUNMAP: a tool for automatic topology selection and generation for NoCs. Proceedings of Design Automation Conference (DAC '04) 2004 San Diego, Calif, USA 914 919
-
(2004)
Proceedings of Design Automation Conference (DAC '04)
, pp. 914-919
-
-
Murali, S.1
De Micheli, G.2
-
16
-
-
27944435722
-
A low latency router supporting adaptivity for on-chip interconnects
-
vijay@cse.psu.edu theochar@cse.psu.edu dpark@cse.psu.edu jmkim@cse.psu.edu das@cse.psu.edu Anaheim, Calif, USA
-
J. Kim jmkim@cse.psu.edu D. Park dpark@cse.psu.edu T. Theocharides theochar@cse.psu.edu N. Vijaykrishnan vijay@cse.psu.edu C. R. Das das@cse.psu.edu A low latency router supporting adaptivity for on-chip interconnects. Proceedings of the 42nd Design Automation Conference (DAC '05) 2005 Anaheim, Calif, USA 559 564
-
(2005)
Proceedings of the 42nd Design Automation Conference (DAC '05)
, pp. 559-564
-
-
Kim, J.1
Park, D.2
Theocharides, T.3
Vijaykrishnan, N.4
Das, C.R.5
-
22
-
-
0034245046
-
Towards achieving energy-efficiency in presence of deep submicron noise
-
R. Hegde N. R. Shanbhag Towards achieving energy-efficiency in presence of deep submicron noise. IEEE Transactions on VLSI Systems 8 2000 4 379 391
-
(2000)
IEEE Transactions on VLSI Systems
, vol.8
, Issue.4
, pp. 379-391
-
-
Hegde, R.1
Shanbhag, N.R.2
-
23
-
-
20444467586
-
Error control schemes for on-chip communication links: The energy-reliability tradeoff
-
lbenini@deis.unibo.it dbertozzi@deis.unibo.it nanni@stanford.edu
-
D. Bertozzi dbertozzi@deis.unibo.it L. Benini lbenini@deis.unibo.it G. De Micheli nanni@stanford.edu Error control schemes for on-chip communication links: the energy-reliability tradeoff. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24 6 2005 818 831
-
(2005)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.6
, pp. 818-831
-
-
Bertozzi, D.1
Benini, L.2
De Micheli, G.3
-
27
-
-
4544376708
-
Fault tolerant algorithms for network-on-chip interconnect
-
link@cse.psu.edu pirretti@cse.psu.edu vijay@cse.psu.edu Lafayette, La, USA
-
M. Pirretti pirretti@cse.psu.edu G. M. Link link@cse.psu.edu R. R. Brooks N. Vijaykrishnan vijay@cse.psu.edu M. Kandemir M. J. Irwin Fault tolerant algorithms for network-on-chip interconnect. Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI '04) Lafayette, La, USA 2004 46 51
-
(2004)
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI '04)
, pp. 46-51
-
-
Pirretti, M.1
Link, G.M.2
Brooks, R.R.3
Vijaykrishnan, N.4
Kandemir, M.5
Irwin, M.J.6
-
28
-
-
27944452666
-
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
-
petel@ida.liu.se sorma@ida.liu.se zebpe@ida.liu.se Anaheim, Calif, USA
-
S. Manolache sorma@ida.liu.se P. Eles petel@ida.liu.se Z. Peng zebpe@ida.liu.se Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC. Proceedings of the 42nd Design Automation Conference (DAC '05) 2005 Anaheim, Calif, USA 266 269
-
(2005)
Proceedings of the 42nd Design Automation Conference (DAC '05)
, pp. 266-269
-
-
Manolache, S.1
Eles, P.2
Peng, Z.3
-
33
-
-
34247272634
-
-
http://www.ocpip.org/
-
-
-
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