Implementing tile-based chip multiprocessors with GALS clocking styles

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 174-179

  Yu, Zhiyi ^a   Baas, Bevan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTI PROCESSORS; COMPUTER DESIGNS; GLOBALLY ASYNCHRONOUS-LOCALLY SYNCHRONOUS; IMPLEMENTATION TECHNIQUES; INTERNATIONAL CONFERENCES; PHYSICAL DESIGNS; SINGLE CHIPS; SINGLE PROCESSORS; SYSTEM ROBUSTNESS;

DATA PROCESSING; MULTIPROCESSING SYSTEMS; SCALABILITY; SYSTEMS ANALYSIS;

ARCHITECTURAL DESIGN;

EID: 35348901308     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380812     Document Type: Conference Paper

References (12)

1. D. Pham, S. Asano, M. Bolliger, M. N. Day, H. P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Riley, D. Shippy, D. Stasiak, M. Suzuoki, M. Wang, J. Warnock, S. Weitzel, D. Wendel, T. Yamazaki, and K. Yazawa, "The design and implementation of a first-generation cell processor," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2005, pp. 184-185.
2. M. B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P. Johnson, W. Lee, A. Saraf, N. Shnidman, V. Strumpen, S. Amarasinghe, and A. Agarwal, "A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2003, pp. 170-171.
3. S. W. Keckler, D. Burger, C. R. Moore, R. Nagarajan, K. Sankaralingam, V. Agarwal, M. S. Hrishikesh, N. Ranganathan, and P. Shivakumar, "A wire-delay scalable microprocessor architecture for high performance systems," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2003, pp. 168-169.
4. K. Mai, T. Paaske, N. Jayasena, R. Ho, W. J. Dally, and M. Horowitz, "Smart memories: A modular reconfigurable architecture," in International Symposium on Computer Architecture (ISCA), June 2000, pp. 161-171.
5. Z. Yu, M. Meeuwsen, R. Apperson, O. Sattari, M. Lai, J. Webb, E. Work, T. Mohsenin, M. Singh, and B. Baas, "An asynchronous array of simple processors for DSP applications," in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2006, pp. 428-429.
6. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture," in IEEE International Conference on Design Automation (DAC), June 2003, pp. 338-342.
7. G. Semeraro, G. Magklis, R. Balasubramonian, D. Albonesi, S. Dwarkadas, and M. L. Scott, "Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling," in International Symposium on High-Performance Computer Architecture (HPCA), 2002, pp. 29-40.
8. Ryan W. Apperson, "A dual-clock FIFO for the reliable transfer of high-throughput data between unrelated clock domains," M.S. thesis, University of California, Davis, Sept. 2004.
9. J.M.Rabaey, Digital Integrated Circuits - A Design Perspective, Prentice-Hall International, Inc, first edition, 1998.
10. M. Fukase, T. Sato, R. Egawa, and T. Nakamura, "Scaling up of wave pipelines," in International Conference on VLSI Design, Jan. 2001, pp. 439-445.
11. P. Cocchini, "Concurrent Flip-Flop and repeater insertion for high performance integrated circuits," in IEEE International Conference on Computer Aided Design (ICCAD), Nov. 2002, pp. 268-273.
12. B. R. Quinton, M. R. Greenstreet, and S. J.E. Wilton, "Asynchronous IC interconnect network design and implementation using a standard ASIC flow," in IEEE International Conference on Computer Design (ICCD), Oct. 2005, pp. 267-274.