System-level buffer allocation for application-specific networks-on-chip router design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 12, 2006, Pages 2919-2933

  Hu, Jingcao ^a,b,c   Ogras, Umit Y ^a,b   Marculescu, Radu ^a,b  

^a IEEE   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c Tabula Inc   (United States)

Author keywords

Buffer sizing; Design automation; Low power; Networks on chip (NoCs); Optimization

Indexed keywords

BUFFER ALLOCATION; BUFFERING RESOURCES; DESIGN AUTOMATION; NETWORKS ON CHIP (NOC);

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MICROPROCESSOR CHIPS; OPTIMIZATION; ROUTERS;

BUFFER STORAGE;

EID: 33845651403     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.882474     Document Type: Article

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