Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2005, Pages 408-419

  Kumar, Rakesh ^a   Zyuban, Victor ^b   Tullsen, Dean M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASE-LINE ARCHITECTURE; CO-DESIGN; MULTICORE DESIGN; ON-CHIP INTERCONNECTS;

BANDWIDTH; BUFFER STORAGE; HIERARCHICAL SYSTEMS; MICROPROCESSOR CHIPS; OPTIMIZATION;

COMPUTER ARCHITECTURE;

EID: 27544456315     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2005.34     Document Type: Conference Paper

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