Orion: A power-performance simulator for interconnection networks

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2002-January, Issue , 2002, Pages 294-305

  Wang, Hang Sheng ^a   Zhu, Xinping ^a   Peh, Li Shiuan ^a   Malik, Sharad ^a  

^a Princeton University   (United States)

Author keywords

Blades; Energy consumption; Fabrics; Hip; Microprocessors; Multiprocessor interconnection networks; Network servers; Network synthesis; Power system modeling; Switches

Indexed keywords

COMPUTER ARCHITECTURE; ENERGY UTILIZATION; FABRICS; HOT ISOSTATIC PRESSING; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); MICROPROCESSOR CHIPS; SIMULATORS; SWITCHES;

ARCHITECTURAL LEVELS; BLADES; MICRO ARCHITECTURES; NETWORK SERVER; NETWORK SYNTHESIS; PERFORMANCE CHARACTERISTICS; POWER CHARACTERISTIC; POWER SYSTEM MODEL;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 84948976085     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2002.1176258     Document Type: Conference Paper

References (28)

1. P. Bannon. Alpha 21364 (EV7). http://www. eecs. umich. edu/vlsi seminar/f01/slides/bannon. pdf.
2. D. Brooks and M. Martonosi. Value-based clock gating and operation packing: Dynamic strategies for improving processor power and performance. ACM Transactions on Computer Systems, 18(2), 2000.
3. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proc. International Symposium on Computer Architecture, 2000.
4. J. A. Butts and G. S. Sohi. A static power model for architects. In Proc. International Symposium on Microarchitecture, 2000.
5. W. J. Dally. Virtual-channel flow control. IEEE Transactions on Parallel and Distributed Systems, 3(2), 1992.
6. W. J. Dally and C. L. Seitz. The torus routing chip. Journal of Parallel and Distributed Computing, 1(3), 1986.
7. W. J. Dally and B. Towles. Route packets, not wires: Onchip interconnection networks. In Proc. Design Automation Conference, 2001.
8. IBM. IBM InfiniBand 8-port 12x switch. http://www-3. ibm. com/chips/products/infiniband/.
9. M. B. Kamble and K. Ghose. Analytical energy dissipation models for low-power caches. In Proc. International Symposium on Low Power Electronics and Design, 1997.
10. M. Katevenis, P. Vatsolaki, and A. Efthymiou. Pipelined memory shared buffer for VLSI switches. In Proc. Conference on Applications, Technologies, Architectures, and Protocols for Computer Communication, 1995.
11. M.-J. E. Lee, W. J. Dally, and P. Chiang. Low-power areaefficient high-speed I/O circuit techniques. IEEE Journal of Solid-State Circuits, 35(11), 2000.
12. Mellanox Technologies Inc. Mellanox performance, price, power, volume metric (PPPV). http://www. mellanox. com/ products/shared/PPPV. pdf.
13. S. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb. The Alpha 21364 network architecture. IEEE Micro, 22(1), 2002.
14. C. S. Patel, S. M. Chai, S. Yalamanchili, and D. E. Schimmel. Power constrained design of multiprocessor interconnection networks. In Proc. International Conference on Computer Design, 1997.
15. L.-S. Peh andW. J. Dally. A delay model and speculative architecture for pipelined routers. In Proc. International Symposium on High Performance Computer Architecture, 2001.
16. M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli. Addressing the system-on-a-chip interconnect woes through communication-based design. In Proc. Design Automation Conference, 2001.
17. L. Shang, L.-S. Peh, and N. K. Jha. Power-efficient interconnection networks: Dynamic voltage scaling with links. Computer Architecture Letters, 1(2), 2002.
18. P. Stanley-Marbell, M. S. Hsiao, and U. Kremer. A hardware architecture for dynamic performance and energy adaptation. In Proc. Workshop on Power-Aware Computer Systems, 2002.
19. C. B. Stunkel, D. G. Shea, B. Abali, M. G. Atkins, C. A. Bender, D. G. Grice, P. H. Hochschild, D. J. Joseph, B. J. Nathanson, R. A. Swetz, R. F. Stucke, M. Tsao, and P. R. Varker. The SP2 high-performance switch. IBM Systems Journal, 34(2), 1995.
20. Synopsys Corp. PowerCompiler datasheet. http://www. synopsys. com/products/power/power bkg. html.
21. M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, and D. I. August. Microarchitectural exploration with Liberty. In Proc. International Symposium on Microarchitecture, 2002.
22. H.-S. Wang, L.-S. Peh, and S. Malik. A power model for routers: Modeling Alpha 21364 and InfiniBand routers. In Proc. Hot Interconnects 10, 2002.
23. S. J. Wilton and N. P. Jouppi. An enhanced access and cycle time model for on-chip caches. Technical Report 93/5, DEC Western Research Laboratory, 1994.
24. T. T. Ye, L. Benini, and G. D. Micheli. Analysis of power consumption on switch fabrics in network routers. In Proc. Design Automation Conference, 2002.
25. W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. The design and use of SimplePower: A cycle-accurate energy estimation tool. In Proc. Design Automation Conference, 2000.
26. H. Zhang, M. Wan, V. George, and J. Rabaey. Interconnect architecture exploration for low-energy reconfigurable single-chip DSPs. In Proc. IEEE Computer Society Workshop on VLSI, 1999.
27. X. Zhu and S. Malik. A hierarchical modeling framework for on-chip communication architectures. In Proc. International Conference on Computer-Aided Design, 2002.
28. V. Zyuban and P. Kogge. The energy complexity of register files. In Proc. International Symposium on Low Power Electronics and Design, 1998.