Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 349-354

  Liu, Chunsheng ^a   Iyengar, Vikram ^b   Shi, Jiangfan ^a   Cota, Erika ^c  

^a UNIVERSITY OF NEBRASKA LINCOLN   (United States)

^b IBM MICROELECTRONICS   (United States)

^c FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK ON CHIP; ON-CHIP COMMUNICATION NETWORKS; ON-CHIP NETWORKS; POWER CONSTRAINTS; SUBSTANTIAL REDUCTION; TEST APPLICATION TIME; TEST EFFICIENCY; TEST SCHEDULING;

CLOCKS; DATA TRANSFER; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT TESTING; SCHEDULING; SERVERS; VLSI CIRCUITS;

TESTING;

EID: 84886567968     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.66     Document Type: Conference Paper

References (15)

1. C. Aktouf. A Complete Strategy for Testing an On-Chip Multiprocessor Architecture. In IEEE Design & Test of Computers, Vol 19, pp. 18-28, Jan-Feb 2002.
2. M. Benabdenbi, W. Maroufi, and M. Marzouki. CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing. In Journal of Electronic Testing: Theory and Applications, Vol 18, pp. 455-473, Aug. 2002.
3. L. Benini and G. D. Micheli. Networks on Chips: a New SOC Paradigm. In IEEE Computer, Vol 35, pp. 70-78, Jan. 2002.
4. V. Chickermane, P. Gallagher, S. Gregor and T. St. Pierre. A building block BIST methodology for SOC designs: A case study. Proc. International Test Conference, pp. 111-120, 2001.
5. E. Cota, L. Carro, F. Wagner, and M. Lubaszewski. Power-aware NoC Reuse on the Testing of Core-based Systems. Proc. International Test Conference, pp. 612-621, Oct. 2003.
6. J. Duato et al. Interconnection Networks: an Engineering Approach. IEEE Computer Society Press, Los Alamitos, CA, 1997.
7. Koranne. Formulating SoC Test Scheduling as a Network Transportation Problem. In IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol 21, pp. 1517-1525, Dec. 2002.
8. E. Larsson and Z. Peng. A reconfigurable power-conscious core wrapper and its application to SOC test scheduling. Proc. International Test Conference, pp. 1135-1144, 2003.
9. C. Liu, E. Cota, H. Sharif and D. K. Pradhan. Test scheduling for network-on-chip with BIST and precedence constraints. Proc. International Test Conference, 2004, to appear. (available at http://ceen. unomaha. edu/ceenpeople/cliu/ITC 04. pdf)
10. E. J. Marinissen, V. Iyengar, and K. Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. Proc. International Test Conference, pp. 521-528. Oct. 2002.
11. E. J. Marinissen et al. On IEEE P1500's Standard for Embedded Core Test. In Journal of Electronic Testing: Theory and Applications, Vol 18, pp. 365-383, Aug. 2002.
12. M. Nahvi and A. Ivanov. A Packet Switching Communicationbased Test Access Mechanism for System Chips. Proc. IEEE European Test Workshop, pp. 81-86, 2001.
13. W. Zou, S. Reddy, I. Pomeranz, and Y. Huang. SOC Test Scheduling Using Simulated Annealing. Proc. VLSI Test Symposium, pp. 325-330, Apr. 2003.
14. B. Vermeulen, J. Dielissen, K. Goossens, and C. Ciordas. Bringing Communication Networks On-Chip: The Test and Verification Implications. In IEEE Communications Magazine, Vol 41, pp. 74-81, Sept. 2003.
15. C. Zeferino and A. Susin. SoCIN: A Parametric and Scalable Network-on-Chip. Proc. Symposium on Integrated Circuits and Systems Design, pp. 121-126, Sept. 2003.