Bandwidth-constrained mapping of cores onto NoC architectures

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 896-901

  Murali, Srinivasan ^a   De Micheli, Giovanni ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Bandwidth; Cores; Mapping; Networks on Chips; Routing; Systems on Chips

Indexed keywords

CORES; NETWORKS ON CHIPS; ROUTING; SYSTEMS ON CHIPS; BANDWIDTH CONSTRAINT; BANDWIDTH REQUIREMENT; BANDWIDTH-CONSTRAINED; COMMUNICATION DELAYS; DETERMINISTIC ROUTING; MESH-BASED NETWORKS; TYPICAL APPLICATION; VIDEO PROCESSING APPLICATIONS;

ALGORITHMS; BANDWIDTH; COMPUTER SIMULATION; CONSTRAINT THEORY; DATA TRANSFER; DIGITAL SIGNAL PROCESSING; INTERCONNECTION NETWORKS; MONOLITHIC INTEGRATED CIRCUITS; PACKET SWITCHING; ROUTERS; EXHIBITIONS; LOGIC DESIGN; VIDEO SIGNAL PROCESSING;

COMPUTER SYSTEMS; TELECOMMUNICATION SYSTEMS;

EID: 3042567207     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269002     Document Type: Conference Paper

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