A power and performance model for network-on-chip architectures

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 1250-1255

  Banerjee, Nilanjan ^a   Vellanki, Praveen ^a   Chatha, Karam S ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER ALLOCATION; NETWORK-ON-CHIP ARCHITECTURE; ROUTING ALGORITHMS; DESIGN SPACE EXPLORATION; INTERCONNECTION ARCHITECTURE; LEAKAGE POWER CONSUMPTION; NANOSCALE ARCHITECTURES; NETWORK-ON-CHIP ARCHITECTURES; PERFORMANCE TRADE-OFF; REGISTER TRANSFER LEVEL; SYSTEM-LEVEL PERFORMANCE;

ALGORITHMS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; ROUTERS; EXHIBITIONS; VLSI CIRCUITS;

COMPUTER NETWORKS; DESIGN;

EID: 3042565282     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269067     Document Type: Conference Paper

References (12)

1. D. Sylvester and K. Keutzer. "A Global Wiring Paradign for Deep Submicron Design". IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pages 242-252, February 2000.
2. R.Ho, K. Mai and M. Horowitz. "The Future of Wires". Proceedings of IEEE, pages 490-504, April 2001.
3. J. Davis and D. Meindl. "Compact Distributed RLC Interconnect Models - Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multilevel Networks". IEEE Transactions on Electron Devices, 47(11):2078-2087, November 2000.
4. D. Sylvester and K. Keutzer. "Impact of Small Process Geometries on Microarchitectures in Systems on a Chip". Proceedings of the IEEE, pages 467-484, April 2001.
5. William J. Dally and Brian Towles. "Route Packet, Not Wires: On-Chip Interconnection Networks". In Proceedings of DAC, June 2002.
6. Luca Benini and Giovanni De Micheli. "Networks on Chips: A New SoC Paradigm". IEEE Computer, pages 70-78, January 2002.
7. A.G. Wassal and M.A. Hasan. "Low-power system-level design of VLSI packet switching fabrics". IEEE Transactions on CAD, 20:723-738, June 2001.
8. Terry T. Ye, Luca Benini and Giovanni De Micheli. "Analysis of Power Consumption on Switch Fabrics in Network Routers". In Proceedings of DAC, 2002.
9. H-S Wang, L-S Peh and S. Malik. "Orion: A Power-Performance Simulator for Interconnection Network". In International Symposium on Microarchitecture, Istanbul, Turkey, November 2002.
10. P. Sotiriadis and A. Chandrakasan. "A Bus Energy Model for Deep Sub-micron Technology".
11. Berkeley Predictive Technology Modeling. http://www-device.eecs.berkely. edu/ptm. Technical report.
12. J. Duato, S. Yalamanchili, L. Ni "Interconnection Networks, an Engineering Approach". IEEE Computer Society, 1997.