Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 1090-1095

  Sheibanyrad, A ^a   Miro Panades, I ^b   Greiner, A ^a  

^a SORBONNE UNIVERSITÉ   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CLUSTERING ALGORITHMS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; NETWORK ARCHITECTURE; PACKET NETWORKS; SILICON; SPICE;

MULTI PROCESSORS SYSTEMS; NETWORK ON CHIP; SYSTEMATIC COMPARISON;

MICROPROCESSOR CHIPS;

EID: 34548316907     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364439     Document Type: Conference Paper

References (25)

1. L. Benini, G. De Micheli, "Networks on chip: a new SoC paradigm", IEEE Computer, vol. 35, no. 1, Jan. 2002
2. D. M. Chapiro, "Globally-Asynchronous Locally-Synchronous systems", PhD thesis, Stanford University, 1984
3. S. G. Pestana, E. Rijpkema, A. Rǎdulescu, K. Goossens, O. P. Gangwal, "Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach", DATE 2004
4. P. Wielage, K. Goossens, "Networks on Silicon: Blessing or Nightmare?", DSD 2002
5. J. Sparsø, "Future Networks-on-Chip; will they be Synchronous or Asynchronous?" (Invited talk), SSoCC 2004
6. P. Guerrier, A. Greiner. "A generic architecture for on chip packet-switched interconnections", DATE 2000
7. A. Adriahantenaina, A. Greiner, "Micro-network for SoC: Implementation of a 3 2-port SPIN network?', DATE 2003
8. W. J. Dally, B. Towles, "Route packets, not wires: on-chip interconnection networks", DAC 2001
9. J. Dielissen, A. Rǎdulescu, K. Goossens, E. Rijpkema, "Concepts and Implementation of the Philips Network-on-Chip", IP-SOC 2003
10. M. Dall'Osso, G Biccari, L. Giovannini, D. Bertozzi, L. Benini, "xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs", ICCD 2003
11. M. Millberg, E. Nilsson, R. Thid, A. Jantsch, "Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip", DATE 2004
12. J. Bainbridge, S. Furber, "Chain: A Delay-Insensitive Chip Area Interconnect", IEEE Micro, vol. 22, no. 5, September/October 2002
13. T. Bjerregaard, J. Sparse, "A router architecture for connection-oriented service guarantees in the MANGO clockless Network-on-Chip", DATE 2005
14. D. (R.) Rostislav, V. Vishnyakov, E. Friedman, R. Ginosar, "An Asynchronous Router for Multiple Service Levels Networks on Chip", ASYNC 2005
15. E. Beigne, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin, "An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework', ASYNC 2005
16. T. Felicijan, S. B. Furber, "An Asynchronous On-Chip Network Router with Quality-of-Service (QoS) Support', SOCC 2004
17. I. Miro Panades, A. Greiner, A. Sheibanyrad, "A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach", Nano-Net 2006
18. I. Miro Panades, "Buffer memory control device (Dispositif de commande d'une mémoire tampon)", Patent pending
19. A. Sheibanyrad, A. Greiner, "Two Efficient Synchronous Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures", PATMOS 2006
20. R. Ho, K. W. Mai, M. A. Horowitz, "The future of wires", IEEE, vol. 89, no. 4, April 2001
21. http://www-asim.lip6.fr/recherche/coriolis/
22. http://www-asim.lip6.fr/recherche/alliance/
23. T. T. Ye, G. De Micheli, L. Benini, "Analysis of power consumption on switch fabrics in network routers", DAC 2002
24. L. Benini, P. Siegel, G. De Micheli, "Saving Power by Synthesizing Gated Clocks for Sequential Circuits", IEEE Design & Test, vol. 11, no. 4, October 1994
25. W. J. Bainbridge, W. B. Toms, D. A. Edwards, S. B. Furber, "Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes", ASYNC 2003