Reliability support for on-chip memories using Networks-on-Chip

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 389-396

  Angiolini, Federico ^a   Atienza, David ^b,d   Murali, Srinivasan ^b,c   Benins, Luca ^a   De Micheli, Giovanni ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b EPFL   (Switzerland)

^c STANFORD UNIVERSITY   (United States)

^d UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; ELECTRIC FAULT CURRENTS; ELECTRIC NETWORK TOPOLOGY; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS;

CASE STUDIES; COMPUTER DESIGNS; CRITICAL DATA; CRITICAL ELEMENTS; DESIGN CHALLENGES; FAULT TOLERANT SYSTEMS; FAULT-TOLERANT; INTERMITTENT FAULTS; INTERNATIONAL CONFERENCES; MULTIMEDIA APPLICATIONS; NETWORK-ON-CHIP; NETWORKS ON CHIPS; ON-CHIP MEMORIES; PERFORMANCE IMPACTS; PHYSICAL LIMITS; RUN-TIME; SOFTWARE INTERVENTION; SYSTEM LEVELS; SYSTEMS-ON-CHIPS;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 49749100084     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380846     Document Type: Conference Paper

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