Equalized interconnects for on-chip networks: Modeling and optimization framework

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 552-559

  Byungsub, Kim ^a   Stojanović, Vladimir ^a  

^a Massachusetts Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSERVATION; DESIGN; ELECTRIC NETWORK TOPOLOGY; ENERGY EFFICIENCY; INTERCONNECTION NETWORKS; OPTICAL INTERCONNECTS; OPTIMIZATION; SPACE RESEARCH; STANDARDS; THROUGHPUT; WIRELESS TELECOMMUNICATION SYSTEMS;

APPROPRIATE MODELS; ARCHITECTURAL OPTIMIZATION; COMPUTER-AIDED DESIGN; CROSS-LAYER MODELING; DESIGN SPACE EXPLORATION; ENERGY-EFFICIENT; ENERGY-PER-BIT; INTERNATIONAL CONFERENCES; LINK DESIGN; LINK PERFORMANCE; MODELING FRAMEWORK; ON-CHIP INTERCONNECTS; ON-CHIP NETWORKS; OPTIMIZATION FRAMEWORK; ORDERS-OF-MAGNITUDE; POINT DESIGN; SPEED UPS; STANDARD MACHINES; WIRE PARAMETERS;

MACHINE DESIGN;

EID: 50249133214     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397323     Document Type: Conference Paper

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