A statistical traffic model for on-chip interconnection networks

Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS

Volumn , Issue , 2006, Pages 104-116

  Soteriou, Vassos ^a   Wang, Hangsheng ^b   Peh, Li Shiuan ^a  

^a Princeton University   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTI-PROCESSORS (CMPS); DESIGN SPACE EXPLORATION; NETWORK TRAFFIC MODELING; ON-CHIP INTERCONNECTION NETWORK; SCALABLE COMMUNICATION; SPATIAL AND TEMPORAL VARIATION; SPATIOTEMPORAL CHARACTERISTICS; TRAFFIC CHARACTERISTICS;

EMBEDDED SYSTEMS; HTTP; INTERNET PROTOCOLS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; SPACE RESEARCH; TELECOMMUNICATION SYSTEMS;

COMPUTER SIMULATION;

EID: 84891462850     PISSN: 15267539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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