Implementation and evaluation of on-chip network architectures

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 477-484

  Gratz, Paul ^a   Kim, Changkyu ^b   McDonald, Robert ^b   Keckler, Stephen W ^b   Burger, Doug ^b  

^a The University of Texas at Austin   (United States)

^b University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEXITY REDUCTION; COMPUTER DESIGNS; HIGH-BANDWIDTH; INTERNATIONAL CONFERENCES; L2 CACHE; LINK BANDWIDTHS; LOW-LATENCY; MESH NETWORKS; NETWORKED ARCHITECTURES; OFF-CHIP; ON-CHIP INTERCONNECTS; ON-CHIP NETWORK; OVERALL PERFORMANCE; VIRTUAL CHANNELS;

CHLORINE COMPOUNDS; ELECTRIC NETWORK TOPOLOGY; MESH GENERATION; OPTICAL INTERCONNECTS; TELECOMMUNICATION SYSTEMS;

BANDWIDTH;

EID: 36348975404     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380859     Document Type: Conference Paper

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