Power-aware communication optimization for networks-on-chips with voltage scalable links

Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004

Volumn , Issue , 2004, Pages 170-175

  Shin, Dongkun ^a   Kim, Jihong ^a  

^a Seoul National University   (South Korea)

Author keywords

Low power design; Network on chip; Real time systems

Indexed keywords

ALGORITHMS; COMMUNICATION SYSTEMS; COMPUTER NETWORKS; ELECTRIC POTENTIAL; REAL TIME SYSTEMS; ROUTERS; SCHEDULING; TELECOMMUNICATION LINKS;

LOW-POWER DESIGN; NETWORKS-ON-CHIPS; POWER-AWARE COMMUNICATION; VOLTAGE SCALABLE LINKS;

MICROPROCESSOR CHIPS;

EID: 16244370420     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1016720.1016763     Document Type: Conference Paper

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