A low complexity heuristic for design of custom network-on-chip architectures

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Srinivasan, Krishnan ^a   Chatha, Karam S ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; ELECTRIC POWER UTILIZATION; HEURISTIC METHODS; OPTIMIZATION; SYSTEMS ANALYSIS;

NETWORK GENERATION; NOC ARCHITECTURES; PHYSICAL DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 34047167070     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.244034     Document Type: Conference Paper

References (21)

1. K. Srinivasan, K.S. Chatha, and G. Konjevod. "Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures". Accepted at IEEE Transactions on VLSI, In Press.
2. W. J. Dally and B. Towles. "Route Packet, Not Wires: On-Chip Interconnection Networks". In Proceedings of DAC, June 2002.
3. L. Benini and G. De Micheli. "Networks on Chips: A New SoC Paradigm". IEEE Computer, pages 70-78, January 2002.
4. M.B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P. Johnson, J-W Lee, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen M. Frank, S. Amarasinghe, and A. Agrawal. "The RAW Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs". IEEE Micro, pages 25-35, March-April 2002.
5. A. Jalabert, S. Murali, L. Benini, and G. De Micheli. "xpipesCompiler: A tool for instantiating application specific Networks on Chip". In DATE, 2004.
6. Nilanjan Banerjee, Praveen Vellanki, and Karam S. Chatha. "A Power and Performance Model for Network-on-Chip Architectures". DATE, pages 68-75, 2004.
7. S. Murali, L. Benini, and G. De Micheli. "Mapping and Physical Planning of Networks-on-Chip Architectures with Quality-of-Service Guarantees". In Proceedings of ASPDAC, 2005.
8. S. Murali, and G. De Micheli. "Bandwidth-Constrained Mapping of Cores onto NoC Architectures". In DATE, 2004.
9. J. Hu and R. Marculescu. "Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints". In ASP-DAC, 2003.
10. K. Srinivasan, and K. S. Chatha. "A Technique for Low Energy Mapping and Routing in Network-on-Chip Architectures ". In Proceedings of ISLPED, San Diego, CA, USA, August 2005.
11. A. Pinto, L. P. Carloni, and A. L. Sangiovanni-Vincentelli. "Efficient Synthesis of Networks On Chip". In ICCD, 2003.
12. K. Srinivasan, K. S. Chatha, and G. Konjevod. "Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures ". In Proceedings of ICCD, San Jose, USA, October 2004.
13. K. Srinivasan, and K. S. Chatha. "ISIS: A Genetic Algorithm based Technique for Synthesis of On-Chip Interconnection Networks ". In Proceedings of VLSI Design, Calcutta, India, January 2005.
14. K. Srinivasan, and K. S. Chatha. "SAGA: Synthesis Technique for Guaranteed Throughput NoC Architectures". In Proceedings of ASPDAC, Shanghai, China, January 2005.
15. Umit Ogras and Radu Marculescu. "Energy and Performance Driven NoC Communication Architecture Synthesis Using A Decomposition Approach". In DATE, 2005.
16. K. Srinivasan, K. S. Chatha, and G. Konjevod. "An Automated Technique for Topology and Route Generation for Application Specific On-Chip Interconnection Networks". In Proceedings of ICCAD, San Jose, USA, October 2005.
17. S.M Sait and H. Youssef. VLSI Physical Design Automation: Theory and Practice. McGraw-Hill Inc, 1994.
18. P. Chen, and E.S Kuh. "Floorplan Sizing by Linear Programming Approximation". In Proceeding of DAC, Los Angeles, California, June 2000.
19. J.G Kim, and Y.D Kim. "A Linear Programming Based Algorithm for Floorplanning in VLSI Design". IEEE Transactions on CAD, 22(5), 2003.
20. C.M Fiduccia and R.M Mattheyses. "A Linear-Time Heuristic for Improving Network Partitions". In Proceedings of DAC, 1982.
21. W.J. Dally and C.L. Seitz. "Deadlock-free message routing in multiprocessor interconnection networks". "IEEE Transactions on Computers", C-36(5):547-553, 1987.