A technique for low energy mapping and routing in network-on-chip architectures

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2005, Pages 387-392

  Srinivasan, Krishnan ^a   Chatha, Karam S ^a  

^a AZ 85281   (United States)

Author keywords

Automated design; Core mapping; Mesh topology; Network on Chip; Routing

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; ENERGY EFFICIENCY; POWER ELECTRONICS; ROUTERS;

AUTOMATED DESIGN; CARE MAPPING; MESH TOPOLOGY; NETWORK-ON-CHIP;

MICROPROCESSOR CHIPS;

EID: 28444439962     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2005.195552     Document Type: Conference Paper

References (9)

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