Thermal-aware IP visualization and placement for networks-on-chip architecture

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 430-437

  Hung, W ^a   Addo Ouaye, C ^a   Theocharides, T ^a   Xie, Y ^a   Vijaykrishnan, N ^a   Irwin, M J ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; DECODING; ELECTRIC POWER UTILIZATION; NETWORK PROTOCOLS; ROUTERS; TEMPERATURE DISTRIBUTION;

NETWORK-ON-CHIP (NOC); PERFORMANCE GAIN; PROCESSING ELEMENTS (PE); SYSTEM-ON-CHIP (SOC);

PACKET NETWORKS;

EID: 17644418462     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. G. Al-Rawi, J. Cioffi and M. Horowitz., "Optimizing the mapping of LDPC Codes on parallel decoding architectures", Proceedings of the IEEE ITCC, 2001. pp. 578-586.
2. L. Benini and G. De Micheli. Networks on chips: a new SoC paradigm, IEEE Computer, Volume 35, pp. 70-78, January 2002.
3. Guoqiang Chen and Sachin Sapatnekar, "Partition-Driven Standard Cell Thermal Placement", ISPD 2003.
4. C.N. Chu and D.F. Wong, "Matrix Synthesis Approach to Thermal Placement", Proc. Int. Sym. On Physical Design, pp.163-168, 1997.
5. W. J. Dally, B. Towles, "Route packets, not wires: on-chip interconnection networks," Proc. DAC, pp. 684-689, June 2001.
6. R. G. Gallager, "Low-Density Parity-Check Codes", IEEE Transactions on Information Theory, Jan. 1962, pp. 21-28.
7. Goldberg, D.E. Genetic Algorithms in Search, Optimization, and Machine Learning, New York: Addison-Wesley. 1989.
8. J. Hu and R. Marculescu, "Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures", Proceedings of DATE 2003, February 2003.
9. J.Hu, R.Marculescu., "Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints", ASP-DAC 2003.
10. B. Levine et al., "Implementation of Near Shannon Limit Error-Correcting Codes using Reconfigurable Hardware", Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines,2000. Page(s):217-226.
11. T. Theocharides, G. Link et.al., "Evaluating Alternative Implementations for the LDPC Check Node Function", Proceedings of the IEEE International Symposium on VLSI, February 2004.
12. D. Mackay R. Neal, "Near Shannon limit performance of low density parity check codes", IEE Electronics Letters, Vol.33, no. 6, March 1997, pp 457-458.
13. M. M. Mansour and N. R. Shanbag, "Low-Power VLSI Decoder Architectures for LDPC Codes", Proc. of the 2002 International Symposium on Low Power Electronics and Design, Page(s): 284-289.
14. S. Murali and G. De Micheli, "Bandwidth-Constrained Mapping of Cores onto NoC Architectures", Proceedings of DATE'04, February 2004.
15. K. Skadron, T. Abdelzaher, and M. Stan, "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management", In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pp. 17-28, Feb. 2002.
16. J.Schaffer, J. Caruana, L. Eshelman and R.Das, "A study of control parameters affecting online performance of genetic algorithms for function optimization," Proc. of the Third international Conference on Genetic Algorithms, pp.51-60, 1989
17. Kevin Skadron, Mircea R. Stan, Wei Huang, et al., "Temperature-Aware Microarchitecture", ISCA 2003.
18. Ching-Han Tsai and Sung-Mo Kang, "Stand Cell Placement for Even On-Chip Thermal Distribution", ISPD 1999.
19. E. Yeo, B. Nikolic and V. Anantharam, "Architectures and Implementations of Low-Density Parity-Check Decoding Algorithms", invited paper at IEEE International Midwest Symposium on Circuits and Systems, Aug 4-7, 2002.
20. T. Zhang et al, "On Finite Precision Implementation of Low Density Parity Check Codes Decoder", Proc. Of the 2001 IEEE International Symposium on Circuits and Systems.