Robust interfaces for mixed-timing systems with application to latency-insensitive protocols

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 21-26

  Chelcea, T ^a   Nowick, S M ^a  

^a Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CONSTRAINT THEORY; INTERCONNECTION NETWORKS; INTERFACES (MATERIALS); NETWORK PROTOCOLS; SYNCHRONIZATION; THROUGHPUT;

LATENCY-INSENSITIVE PROTOCOLS; ROBUST INTERFACES;

TIMING CIRCUITS;

EID: 0034853842     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378256     Document Type: Conference Paper

References (16)

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12. Micropipelines
13. Pausible clocking: A first step toward heterogeneous systems