An architecture and compiler for scalable on-chip communication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 7, 2004, Pages 711-726

  Liang, Jian ^a   Laffely, Andrew ^b   Srinivasan, Sriram ^c   Tessier, Russell ^a  

^a University of Massachusetts   (United States)

^b Air Force Research Laboratory   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

Communications architecture; On chip interconnect; System on chip (SoC)

Indexed keywords

ADAPTIVE SYSTEMS; BANDWIDTH; COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA TRANSFER; INTELLECTUAL PROPERTY; LARGE SCALE SYSTEMS; MICROPROCESSOR CHIPS; OPTIMIZATION; SIGNAL PROCESSING;

COMMUNICATIONS ARCHITECTURE; MAPPING SOFTWARE; ON-CHIP INTERCONNECT; SYSTEM-ON-CHIP (SOC);

VLSI CIRCUITS;

EID: 3142720340     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.830919     Document Type: Conference Paper

References (36)

1. The International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2001.
2. IDT Peripheral Bus: Intermodule Connection Technology Enables Broad Range of System-Level Integration, IDT Inc., 2000.
3. Wishbone: System-on-Chip (SoC) Interconnect Architecture for Portable IP Cores Revision B.3, Silicore Inc., 2002.
4. Silicon Micronetworks Technical Overview; Sonics Inc., 2002.
5. P. J. Aldworth, "System-on-a-chip bus architecture for embedded applications," in Proc. IEEE Int. Conf. Computer Design, Austin, TX, Oct. 1999, pp. 297-298.
6. D. Flynn, "AMBA: Enabling reusable on-chip design," IEEE Micro., vol. 17, pp. 20-27, July 1997.
7. The CoreConnect Bus Architecture, IBM, Inc., 1999.
8. M. Wan, Y. Ichikawa, D. Lidsky, and J. Rabaey, "An energy-conscious exploration methodology for heterogeneous DSPs," in Proc. IEEE Custom Integrated Circuits Conf., Santa Clara, CA., May 1998, pp. 111-117.
9. W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. ACM/IEEE Design Automation Conf., Las Vegas, NV, June 2001, pp. 684-689.
10. D. Wingard, "Micronetwork-based integration for SOCs," in Proc. ACM/IEEE Design Automation Conf., Las Vegas, NV., June 2001, pp. 673-677.
11. S. Borkar, R. Cohn, G. Cox, T. Gross, H. T. Kung, M. Lam, M. Levine, B. Moore, W. Moore, C. Peterson, J. Susman, J. Sutton, J. Urbanski, and J. Webb, "Supporting systolic and memory communication in iWarp," in Proc. 17th Int. Symp. Computer Architecture, June 1990, pp. 70-81.
12. D. Shoemaker, C. Metcalf, and S. Ward, "NuMesh: An architecture optimized for scheduled communication," J. Supercomputlng, vol. 10, no. 3, pp. 285-302, Aug. 1996.
13. E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal, "Baring it all to software: Raw machines," IEEE Trans. Comput., vol. 30, pp. 86-93, Sept. 1997.
14. W. Lee, R. Barua, M. Frank, D. Srikrishna, J. Babb, V. Sarkar, and S. Amarasinghe, "Space-time scheduling of instruction-level parallelism on a RAW machine," in Proc. 8th ACM Conf. Architectural Support for Programming Languages and Operating Systems, San Jose, CA, Oct. 1998, pp. 46-57.
15. J. Babb, M. Rinard, C. A. Moritz, W. Lee, M. Frank, R. Barua, and S. Amarasinghe, "Parallelizing applications to silicon," in Proc. IEEE Symp. Field-Programmable Custom Computing Machines, Napa, CA, Apr. 1999, pp. 70-80.
16. R. Wilson, R. French, C. Wilson, S. Amarasinghe, J. Anderson, S. Tjing, S. Liao, C. W. Tseng, M. Hall, M. Lam, and J. Hennessy, "SUIF: An infrastructure for research on parallelizing and optimizing compilers," ACM SIGPLAN Notices, vol. 29, no. 12, pp. 31-37, Dec. 1994.
17. J. Babb, R. Tessier, M. Dahl, S. Hanono, and A. Agarwal, "Logic emulation with virtual wires," IEEE Trans. Computer-Aided Design, vol. 16, pp. 609-626, June 1997.
18. K. Keutzer, S. Malik, R. Newton, J. Rabaey, and A. Sangiovanni- Vincentelli, "System-level design: Orthogonalization of concerns and platform-based design," IEEE Trans. Computer-Aided Design, vol. 19, pp. 1523-1543, Dec. 2000.
19. P. Knudsen and J. Madsen, "Integrating communication protocol selection with hardware/software codesign," IEEE Trans. Computer-Aided Design, vol. 18, pp. 1077-1095. Aug. 1999.
20. K. Lahiri, A. Raghunathan, and S. Dey, "Performance analysis of systems with multichannel communication," in Proc. Int. Conf. VLSI Design, Calcutta, India, Jan. 2000, pp. 530-537.
21. R. Dick and N. K. Jha, "MOCSYN: Multiobjective core-based single-chip system synthesis," in Proc. European Conf. Design, Automation and Test, Munich, Germany, Mar. 1999, pp. 263-270.
22. G. DeMicheli and R. Gupta, "Hardware/software codesign," Proc. IEEE, vol. 85, pp. 349-365, Mar. 1997.
23. P. Eles, Z. Peng, K. Kuchcinski, and A. Doboli, "System level hardware/software partitioning based on simulated annealing and tabu search," Des. Automation Embedded Syst., vol. 2, no. 1, pp. 5-32, Jan. 1997.
24. R. Ernst, J. Henkel, and T. Benner, "Hardware software cosynthesis for microcontrollers," IEEE Des. Test Comput., vol. 10, pp. 64-75, Dec. 1993.
25. MIPS R4000 Product Specification, MIPS Corp., 2000.
26. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs. Norvell, MA: Kluwer, 1999.
27. M. Ghanbari, Video Coding: An Introduction to Standard Codecs. London, U.K.: IEE, 1999.
28. D. Kim and G. Stuber, "Performance of multiresolution OFDM on frequency-selective fading channels," IEEE Trans. Veh. Technol., vol. 48, pp. 1740-1746, Sept. 1999.
29. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1999.
30. D. Burger and T. M. Austin, "The SimpleScalar Tool Set, Version 2.0," Univ. Wisconsin, Dept. Comput. Sci., Madison, WI, 1342, 1997.
31. T. Schaffer, A. Stanaski, A. Glaser, and P. Franzon, "The NCSU design kit for IC fabrication through MOSIS," in Proc. Int. Cadence User Group Conf., Austin, TX, Sept. 1998, pp. 71-80.
32. Altera NIOS Processor Handbook, Altera Corp., San Jose, CA, 2003, pp. 28-29.
33. W. Dally and H. Aoki, "Deadlock-free adaptive routing in multicomputer networks using virtual channels," IEEE Trans. Parallel Distrib. Syst., vol. 4, pp. 466-475, Apr. 1993.
34. K. Ryu, E. Shin, and V. Mooney, "A comparison of five different multiprocessor SoC bus architectures," in Proc. EUROMICRO Symp. Digital Systems Design, Warsaw, Poland, Sept. 2001, pp. 202-209.
35. K. Ryu and V. Mooney, "Automated bus generation for multiprocessor SoC design," in Proc. Eur. Conf. Design, Automation and Test, Munich, Germany, Mar. 2003, pp. 282-287.
36. D. Culler, J. P. Singh, and A. Gupta, Parallel Computer Architecture: A Hardware/Software Approach. San Mateo, CA: Morgan Kaufman, 1999.