Physical planning for on-chip multiprocessor networks and switch fabrics

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn 2003-January, Issue , 2003, Pages 97-107

  Ye, Terry Tao ^a   De Micheli, Giovanni ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPLEX NETWORKS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; MULTIPROCESSING SYSTEMS; SWITCHING CIRCUITS; SYSTEMS ANALYSIS; TOPOLOGY;

ASIC ARCHITECTURE; DESIGN CONSTRAINTS; INTERCONNECT NETWORKS; INTERCONNECT WIRES; MULTI PROCESSOR SYSTEMS; ON-CHIP IMPLEMENTATIONS; ON-CHIP MULTIPROCESSOR; PROCESSING ELEMENTS;

NETWORK ARCHITECTURE;

EID: 84942518224     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2003.1212833     Document Type: Conference Paper

References (13)

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