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Volumn 9781441993137, Issue , 2012, Pages 1-151

Error control for network-on-chip links

Author keywords

[No Author keywords available]

Indexed keywords

ERRORS; REVIEWS;

EID: 84931827076     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-1-4419-9313-7     Document Type: Book
Times cited : (17)

References (211)
  • 1
    • 2442653656 scopus 로고    scopus 로고
    • Interconnect limits on gigascale integration (GSI) in the 21st Century
    • Davis AJ et al (2001) Interconnect limits on gigascale integration (GSI) in the 21st Century. Proc IEEE 89:305-324
    • (2001) Proc IEEE , vol.89 , pp. 305-324
    • Davis, A.J.1
  • 2
    • 0000239119 scopus 로고    scopus 로고
    • The challenge of signal integrity in deepsubmicrometer CMOS technology
    • Caignet F, Bendhia DS, Sicard E (2001) The challenge of signal integrity in deepsubmicrometer CMOS technology. Proc IEEE 89:556-573
    • (2001) Proc IEEE , vol.89 , pp. 556-573
    • Caignet, F.1    Bendhia, D.S.2    Sicard, E.3
  • 3
    • 0141837018 scopus 로고    scopus 로고
    • Trends and challenges in VLSI circuit reliability
    • Constantinescu C (2003) Trends and challenges in VLSI circuit reliability. IEEE Micro 23:14-19
    • (2003) IEEE Micro , vol.23 , pp. 14-19
    • Constantinescu, C.1
  • 4
    • 29244444803 scopus 로고    scopus 로고
    • Scaling analysis of multilevel interconnect temperatures for high performance ICs
    • Im S, Srivastava N, Banerjee K, Goodson EK (2005) Scaling analysis of multilevel interconnect temperatures for high performance ICs. IEEE Trans Electron Devices 52:2710-2719
    • (2005) IEEE Trans Electron Devices , vol.52 , pp. 2710-2719
    • Im, S.1    Srivastava, N.2    Banerjee, K.3    Goodson, E.K.4
  • 5
    • 0036612170 scopus 로고    scopus 로고
    • High-frequency characterization of on-chip digital interconnects
    • Kleveland B, Qi X, Madden L et al (2002) High-frequency characterization of on-chip digital interconnects. IEEE J Solid-State Circuits 37:716-725
    • (2002) IEEE J Solid-state Circuits , vol.37 , pp. 716-725
    • Kleveland, B.1    Qi, X.2    Madden, L.3
  • 15
    • 78650879028 scopus 로고    scopus 로고
    • A 40 nm 16-core 128-thread SPARC SoC processor
    • Shin LJ et al (2011) A 40 nm 16-core 128-thread SPARC SoC processor. IEEE J Solid-State Circuits 46:131-144
    • (2011) IEEE J Solid-state Circuits , vol.46 , pp. 131-144
    • Shin, L.J.1
  • 18
    • 9144234352 scopus 로고    scopus 로고
    • Characterization of soft errors caused by single event upsets in CMOS processes
    • Karnick T, Hazucha P, Patel J (2004) Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Trans Depend Secure Comput 1:128-143
    • (2004) IEEE Trans Depend Secure Comput , vol.1 , pp. 128-143
    • Karnick, T.1    Hazucha, P.2    Patel, J.3
  • 19
    • 53349173581 scopus 로고    scopus 로고
    • Modeling and simulation of single-event effects in digital devices and ICs
    • Munteanu D, Autran LJ (2008) Modeling and simulation of single-event effects in digital devices and ICs. IEEE Trans Nucl Sci 55:1854-1878
    • (2008) IEEE Trans Nucl Sci , vol.55 , pp. 1854-1878
    • Munteanu, D.1    Autran, L.J.2
  • 20
    • 0034264975 scopus 로고    scopus 로고
    • Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections
    • Tang TK, Friedman GE (2000) Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections. Integr VLSI J 29:131-165
    • (2000) Integr VLSI J , vol.29 , pp. 131-165
    • Tang, T.K.1    Friedman, G.E.2
  • 22
    • 33747574386 scopus 로고    scopus 로고
    • Analytical modeling and characterization of deep submicron interconnect
    • Sylvester D, Hu C (2001) Analytical modeling and characterization of deep submicron interconnect. Proc IEEE 89:634-664
    • (2001) Proc IEEE , vol.89 , pp. 634-664
    • Sylvester, D.1    Hu, C.2
  • 26
    • 0032204374 scopus 로고    scopus 로고
    • Circuit sensitivity to interconnect variations
    • Lin Z et al (1998) Circuit sensitivity to interconnect variations. IEEE Trans Semiconductor Manuf 11:557-568
    • (1998) IEEE Trans Semiconductor Manuf , vol.11 , pp. 557-568
    • Lin, Z.1
  • 27
    • 34748880817 scopus 로고    scopus 로고
    • The impact of size effects and copper interconnect process variations on the maximum critical path delay of single and multi-core microprocessors
    • Lopez G et al (2007) The impact of size effects and copper interconnect process variations on the maximum critical path delay of single and multi-core microprocessors. In: Proceedings of the international interconnect technology conference, pp 40-42
    • (2007) Proceedings of the International Interconnect Technology Conference , pp. 40-42
    • Lopez, G.1
  • 30
    • 0033719785 scopus 로고    scopus 로고
    • A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance
    • Mehrotra V, Sam LS, Boning D et al (2000) A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. In: Proceedings of the ACM/IEEE design automation conference (DAC), pp 172-175
    • (2000) Proceedings of the ACM/IEEE Design Automation Conference (DAC) , pp. 172-175
    • Mehrotra, V.1    Sam, L.S.2    Boning, D.3
  • 31
    • 33847160814 scopus 로고    scopus 로고
    • Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations
    • Qi X, Lo S, Luo Y et al (2005) Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations. In: IEEE custom integrated circuit conference, pp 309-312
    • (2005) IEEE Custom Integrated Circuit Conference , pp. 309-312
    • Qi, X.1    Lo, S.2    Luo, Y.3
  • 32
    • 20444496778 scopus 로고    scopus 로고
    • Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
    • Ajami HA, Banerjee K, Pedram M (2005) Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans Comput Aided Des Integr Circuits Syst 24:849-861
    • (2005) IEEE Trans Comput Aided des Integr Circuits Syst , vol.24 , pp. 849-861
    • Ajami, H.A.1    Banerjee, K.2    Pedram, M.3
  • 33
    • 0032123090 scopus 로고    scopus 로고
    • Analysis of high-speed interconnects in the presence of electromagnetic interference
    • Khazaka R, Nakhla M (1998) Analysis of high-speed interconnects in the presence of electromagnetic interference. IEEE Trans Microw Theory Tech 46:940-947
    • (1998) IEEE Trans Microw Theory Tech , vol.46 , pp. 940-947
    • Khazaka, R.1    Nakhla, M.2
  • 38
    • 53349091798 scopus 로고    scopus 로고
    • Measurement and analysis of interconnect crosstalk due to single events in a 90 nm CMOS technology
    • Balasubramanian A et al (2008) Measurement and analysis of interconnect crosstalk due to single events in a 90 nm CMOS technology. IEEE Trans Nucl Sci 55:2079-2084
    • (2008) IEEE Trans Nucl Sci , vol.55 , pp. 2079-2084
    • Balasubramanian, A.1
  • 42
    • 34548619862 scopus 로고    scopus 로고
    • Evaluating transient error effects in digital nanometer circuits
    • Zhao C, Bai X, Dey S (2007) Evaluating transient error effects in digital nanometer circuits. IEEE Trans Reliab 56:381-391
    • (2007) IEEE Trans Reliab , vol.56 , pp. 381-391
    • Zhao, C.1    Bai, X.2    Dey, S.3
  • 43
    • 2142815785 scopus 로고    scopus 로고
    • Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
    • Maheshwari A, Burleson W, Tessier R (2004) Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 12:299-311
    • (2004) IEEE Trans Very Large Scale Integr (VLSI) Syst , vol.12 , pp. 299-311
    • Maheshwari, A.1    Burleson, W.2    Tessier, R.3
  • 44
    • 45749130595 scopus 로고    scopus 로고
    • Alpha-particle-induced upsets in advanced CMOS circuits and technology
    • Heidel FD et al (2008) Alpha-particle-induced upsets in advanced CMOS circuits and technology. IBM J Res Dev 52:225-232
    • (2008) IBM J Res Dev , vol.52 , pp. 225-232
    • Heidel, F.D.1
  • 45
    • 33846275799 scopus 로고    scopus 로고
    • Multiple-bit upset in 130 nm CMOS technology
    • Tipton DA et al (2006) Multiple-bit upset in 130 nm CMOS technology. IEEE Trans Nucl Sci 53:3259-3264
    • (2006) IEEE Trans Nucl Sci , vol.53 , pp. 3259-3264
    • Tipton, D.A.1
  • 51
    • 34250849255 scopus 로고    scopus 로고
    • Online reconfigurable self-timed links for fault tolerant NoC
    • Lehtonen T, Liljeberg P, Plosila J (2007) Online reconfigurable self-timed links for fault tolerant NoC. VLSI Des. Article ID 94676:13
    • (2007) VLSI des , pp. 13
    • Lehtonen, T.1    Liljeberg, P.2    Plosila, J.3
  • 52
    • 67650241774 scopus 로고    scopus 로고
    • A multi-wire error correction scheme for reliable and energy efficient SoC links using Hamming product codes
    • Fu B, Ampadu P (2008) A multi-wire error correction scheme for reliable and energy efficient SoC links using Hamming product codes. In: Proceedings of the IEEE international SoC conference (SoCC), pp 59-62
    • (2008) Proceedings of the IEEE International SoC Conference (SoCC) , pp. 59-62
    • Fu, B.1    Ampadu, P.2
  • 53
    • 58149513175 scopus 로고    scopus 로고
    • An energy-efficient multi-wire error control scheme for reliable onchip interconnects using Hamming product codes
    • Fu B, Ampadu P (2008) An energy-efficient multi-wire error control scheme for reliable onchip interconnects using Hamming product codes. VLSI Des Article ID: 109490, 1-14, doi:101155/2008/109490
    • (2008) VLSI des , pp. 1-14
    • Fu, B.1    Ampadu, P.2
  • 54
    • 70349257426 scopus 로고    scopus 로고
    • On hamming product codes with type-II hybrid ARQ for on-chip interconnects
    • Fu B, Ampadu P (2009) On hamming product codes with type-II hybrid ARQ for on-chip interconnects. IEEE Trans Circuits Syst I Reg Papers 56:2042-2054
    • (2009) IEEE Trans Circuits Syst I Reg Papers , vol.56 , pp. 2042-2054
    • Fu, B.1    Ampadu, P.2
  • 59
    • 15844363390 scopus 로고    scopus 로고
    • Simultaneous shielding insertion and net ordering for capacitive and inductive couplingminimization
    • Lepak MK, Xu M, Chen J, He L (2004) Simultaneous shielding insertion and net ordering for capacitive and inductive couplingminimization. ACMTrans Des Autom Electron Syst 3:290-309
    • (2004) ACMTrans des Autom Electron Syst , vol.3 , pp. 290-309
    • Lepak, M.K.1    Xu, M.2    Chen, J.3    He, L.4
  • 66
    • 50549092307 scopus 로고    scopus 로고
    • Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
    • Akl JC, Bayoumi AM (2008) Reducing interconnect delay uncertainty via hybrid polarity repeater insertion. IEEE Trans Very Large Scale Integr (VLSI) Syst 9:1230-1239
    • (2008) IEEE Trans Very Large Scale Integr (VLSI) Syst , vol.9 , pp. 1230-1239
    • Akl, J.C.1    Bayoumi, A.M.2
  • 74
    • 0034795679 scopus 로고    scopus 로고
    • Two schemes to reduce interconnect delay in bi-directional and unidirectional buses
    • Nose K, Sakurai T (2001) Two schemes to reduce interconnect delay in bi-directional and unidirectional buses. In: Proceedings of VLSI symposium, pp 193-194
    • (2001) Proceedings of VLSI Symposium , pp. 193-194
    • Nose, K.1    Sakurai, T.2
  • 76
    • 0142227162 scopus 로고    scopus 로고
    • Coupling delay optimization by temporal decorrelation using dual threshold voltage technology
    • Kim WK, Jung OS, Kim T (2003) Coupling delay optimization by temporal decorrelation using dual threshold voltage technology. IEEE Trans Very Large Scale Integr (VLSI) Syst 5:879-887
    • (2003) IEEE Trans Very Large Scale Integr (VLSI) Syst , vol.5 , pp. 879-887
    • Kim, W.K.1    Jung, O.S.2    Kim, T.3
  • 79
    • 50549094505 scopus 로고    scopus 로고
    • Skewed repeater bus: A low power scheme for on-chip bus
    • Ghoneima M et al (2006) Skewed repeater bus: a low power scheme for on-chip bus. IEEE Trans Circuits Syst I Fund Theor Appl 7:1904-19106
    • (2006) IEEE Trans Circuits Syst I Fund Theor Appl , vol.7 , pp. 1904-19106
    • Ghoneima, M.1
  • 80
    • 0036179950 scopus 로고    scopus 로고
    • Decoupling capacitance allocation and its application to power supply noise aware floorplanning
    • Zhao S, Roy K, Koh KC (2002) Decoupling capacitance allocation and its application to power supply noise aware floorplanning. IEEE Trans Computer-Aided Des Integr Circuits Syst 1:8-92
    • (2002) IEEE Trans Computer-aided des Integr Circuits Syst , vol.1 , pp. 8-92
    • Zhao, S.1    Roy, K.2    Koh, K.C.3
  • 87
    • 4043150092 scopus 로고    scopus 로고
    • Xpipes: A network-on-chip architecture for gigascale systems-onchip
    • Bertozzi D, Benini L (2004) Xpipes: a network-on-chip architecture for gigascale systems-onchip. IEEE Circuits Syst Mag 4:18-31
    • (2004) IEEE Circuits Syst Mag , vol.4 , pp. 18-31
    • Bertozzi, D.1    Benini, L.2
  • 92
    • 29144534264 scopus 로고    scopus 로고
    • Low power and fault tolerant encoding methods for on-chip data transfer in practical applications
    • Komatsu S, Fujita M (2005) Low power and fault tolerant encoding methods for on-chip data transfer in practical applications. IEICE Trans Fund E88-A (12):3282-3289
    • (2005) IEICE Trans Fund , vol.E88-A , Issue.12 , pp. 3282-3289
    • Komatsu, S.1    Fujita, M.2
  • 100
    • 70350721965 scopus 로고    scopus 로고
    • Adaptive error control for nanometer scale NoC links
    • Special issue on advances in nanoelectronics circuits and systems
    • Yu Q, Ampadu P (2009) Adaptive error control for nanometer scale NoC links. IET Comput Digit Tech 6:643-659, Special issue on advances in nanoelectronics circuits and systems
    • (2009) IET Comput Digit Tech , vol.6 , pp. 643-659
    • Yu, Q.1    Ampadu, P.2
  • 101
    • 77953346386 scopus 로고    scopus 로고
    • Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects
    • Fu B, Ampadu P (2010) Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects. IET Comput Digit Tech 3:251-261
    • (2010) IET Comput Digit Tech , vol.3 , pp. 251-261
    • Fu, B.1    Ampadu, P.2
  • 103
    • 0021660523 scopus 로고
    • Automatic-repeat-request error-control schemes
    • Lin S et al (1984) Automatic-repeat-request error-control schemes. IEEE Commun Mag 12:5-17
    • (1984) IEEE Commun Mag , vol.12 , pp. 5-17
    • Lin, S.1
  • 107
    • 0018434238 scopus 로고
    • Improvements in block-retransmission schemes
    • Metzner JJ (1979) Improvements in block-retransmission schemes. IEEE Trans Commun 2:524-532
    • (1979) IEEE Trans Commun , vol.2 , pp. 524-532
    • Metzner, J.J.1
  • 110
    • 33646015987 scopus 로고    scopus 로고
    • Synergistic processing in Cell's multicore architecture
    • Gschwind M, Hofstee H, Flachs B et al (2006) Synergistic processing in Cell's multicore architecture. IEEE Micro 26:10-24
    • (2006) IEEE Micro , vol.26 , pp. 10-24
    • Gschwind, M.1    Hofstee, H.2    Flachs, B.3
  • 113
    • 85025582412 scopus 로고    scopus 로고
    • IBMCoreConnect specification. http://www.ibm.com/chips/techlib/techlib.nsf/product families/CoreConnect-Bus-Architecture
    • IBMCoreConnect specification1
  • 117
    • 78650922410 scopus 로고    scopus 로고
    • A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling
    • Howard J et al (2011) A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling. IEEE J Solid-State Circuits 46:173-183
    • (2011) IEEE J Solid-state Circuits , vol.46 , pp. 173-183
    • Howard, J.1
  • 118
    • 24144461667 scopus 로고    scopus 로고
    • Performance evaluation and design trade-offs for network-on-chip interconnect architectures
    • Pande PP, Grecu C, Ivanov A, Saleh R (2005) Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans Comput 54:1025-1040
    • (2005) IEEE Trans Comput , vol.54 , pp. 1025-1040
    • Pande, P.P.1    Grecu, C.2    Ivanov, A.3    Saleh, R.4
  • 120
    • 36849030305 scopus 로고    scopus 로고
    • On-chip interconnection architecture of the tile processor
    • Wentzlaff D et al (2007) On-chip interconnection architecture of the tile processor. IEEE Micro 27:15-31
    • (2007) IEEE Micro , vol.27 , pp. 15-31
    • Wentzlaff, D.1
  • 121
    • 36849013038 scopus 로고    scopus 로고
    • On-chip interconnection networks of the TRIPS chip
    • Gratz P, Kim C, Sankaralingam K, Hanson H et al (2007) On-chip interconnection networks of the TRIPS chip. IEEE Micro 27:41-50
    • (2007) IEEE Micro , vol.27 , pp. 41-50
    • Gratz, P.1    Kim, C.2    Sankaralingam, K.3    Hanson, H.4
  • 123
    • 36849096008 scopus 로고    scopus 로고
    • Architecture of the scalable communications core's network on chip
    • Ilitzky AD, Hoffman DJ, Chun A, Esparza PB (2007) Architecture of the scalable communications core's network on chip. IEEE Micro 27:62-74
    • (2007) IEEE Micro , vol.27 , pp. 62-74
    • Ilitzky, A.D.1    Hoffman, D.J.2    Chun, A.3    Esparza, P.B.4
  • 124
    • 0034846659 scopus 로고    scopus 로고
    • Addressing the system-on-a-chip interconnect woes through communicationbased design
    • Sgroi M et al. (2001) Addressing the system-on-a-chip interconnect woes through communicationbased design. In: Proceedings of 38th Design Automation Conference (DAC), pp 667-672
    • (2001) Proceedings of 38th Design Automation Conference (DAC) , pp. 667-672
    • Sgroi, M.1
  • 135
    • 36849030305 scopus 로고    scopus 로고
    • On-chip interconnection architecture of the tile processor
    • Wentzla D, Griffin P, Hoffmann H et al (2007) On-chip interconnection architecture of the tile processor. IEEE Micro 27:15-31
    • (2007) IEEE Micro , vol.27 , pp. 15-31
    • Wentzla, D.1    Griffin, P.2    Hoffmann, H.3
  • 138
    • 33745800231 scopus 로고    scopus 로고
    • A survey of research and practices of network-on-chip
    • Bjerregaard T, Mahadevan S (2006) A survey of research and practices of network-on-chip. Acm Comput Surv 38:1-51
    • (2006) Acm Comput Surv , vol.38 , pp. 1-51
    • Bjerregaard, T.1    Mahadevan, S.2
  • 140
    • 4043150092 scopus 로고    scopus 로고
    • Xpipes: A network-on-chip architecture for gigascale systems-onchip
    • Bertozzi D, Benini L (2004) Xpipes: a network-on-chip architecture for gigascale systems-onchip. IEEE Circuits Syst Mag 4:18-31
    • (2004) IEEE Circuits Syst Mag , vol.4 , pp. 18-31
    • Bertozzi, D.1    Benini, L.2
  • 154
    • 70350721965 scopus 로고    scopus 로고
    • Adaptive error control for nanometer scale NoC links
    • Special issue on advances in nanoelectronics circuits and systems
    • Yu Q, Ampadu P (2009) Adaptive error control for nanometer scale NoC links. IET Comput Digit Tech 3:643-659 (Special issue on advances in nanoelectronics circuits and systems)
    • (2009) IET Comput Digit Tech , vol.3 , pp. 643-659
    • Yu, Q.1    Ampadu, P.2
  • 155
    • 34250849255 scopus 로고    scopus 로고
    • Online reconfigurable self-timed links for fault tolerant NoC, VLSI Design
    • Lehtonen T, Liljeberg P, Plosila J (2007) Online reconfigurable self-timed links for fault tolerant NoC, VLSI Design. Article ID 94676:13
    • (2007) Article ID
    • Lehtonen, T.1    Liljeberg, P.2    Plosila, J.3
  • 157
    • 40949110161 scopus 로고    scopus 로고
    • Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding
    • Special issue on defect and fault tolerance
    • Gangly A, Pande PP, Belter B, Grecu C (2008) Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding. J Electron Tes: Theory Apple (JETTA), 67-81 (Special issue on defect and fault tolerance)
    • (2008) J Electron Tes: Theory Apple (JETTA) , pp. 67-81
    • Gangly, A.1    Pande, P.P.2    Belter, B.3    Grecu, C.4
  • 158
    • 70350622990 scopus 로고    scopus 로고
    • Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
    • Gangly A, Pande PP, Belter B (2009) Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects. IEEE Trans VLSI Syst 17:1626-1639
    • (2009) IEEE Trans VLSI Syst , vol.17 , pp. 1626-1639
    • Gangly, A.1    Pande, P.P.2    Belter, B.3
  • 165
    • 0026852964 scopus 로고
    • High speed parallel CRC circuits in VLSI
    • Pei BT, Zukowski C (1992) High speed parallel CRC circuits in VLSI. IEEE Trans Commun 40:653-657
    • (1992) IEEE Trans Commun , vol.40 , pp. 653-657
    • Pei, B.T.1    Zukowski, C.2
  • 166
    • 0035329161 scopus 로고    scopus 로고
    • A systematic approach for parallel CRC computations
    • Shieh DM, Sheu HM, Chen HC, Lo FH (2001) A systematic approach for parallel CRC computations. J Inf Sci Eng 17:445-461
    • (2001) J Inf Sci Eng , vol.17 , pp. 445-461
    • Shieh, D.M.1    Sheu, H.M.2    Chen, H.C.3    Lo, F.H.4
  • 167
    • 0015095237 scopus 로고
    • Inversionless decoding of binary BCH codes
    • Burton OH (1971) Inversionless decoding of binary BCH codes. IEEE Trans Inf Theory 17:464-466
    • (1971) IEEE Trans Inf Theory , vol.17 , pp. 464-466
    • Burton, O.H.1
  • 168
    • 0001174154 scopus 로고
    • Polynomial codes over certain finite fields
    • Reed SI, Solomon G (1960) Polynomial codes over certain finite fields. J Soc Ind Appl Math 8:300-304
    • (1960) J Soc Ind Appl Math , vol.8 , pp. 300-304
    • Reed, S.I.1    Solomon, G.2
  • 171
    • 0032140566 scopus 로고    scopus 로고
    • Near-optimum decoding of product codes: Block turbo codes
    • Pyndiah R (1998) Near-optimum decoding of product codes: block turbo codes. IEEE Trans Commun 46:1003-1010
    • (1998) IEEE Trans Commun , vol.46 , pp. 1003-1010
    • Pyndiah, R.1
  • 172
    • 70349257426 scopus 로고    scopus 로고
    • On hamming product codes with type-II hybrid ARQ for on-chip interconnects
    • Fu B, Ampadu P (2009) On hamming product codes with type-II hybrid ARQ for on-chip interconnects. IEEE Trans Circuits Syst I, Reg Papers 9:2042-2054
    • (2009) IEEE Trans Circuits Syst I, Reg Papers , vol.9 , pp. 2042-2054
    • Fu, B.1    Ampadu, P.2
  • 181
    • 58149513175 scopus 로고    scopus 로고
    • An energy-efficient multi-wire error control scheme for reliable onchip interconnects using Hamming product codes
    • Fu B, Ampadu P (2008) An energy-efficient multi-wire error control scheme for reliable onchip interconnects using Hamming product codes. VLSI Des 2008:1-14. doi:101155/2008/109490
    • (2008) VLSI des , vol.2008 , pp. 1-14
    • Fu, B.1    Ampadu, P.2
  • 182
    • 70349257426 scopus 로고    scopus 로고
    • On hamming product codes with type-II hybrid ARQ for on-chip interconnects
    • Fu B, Ampadu P (2009) On hamming product codes with type-II hybrid ARQ for on-chip interconnects. IEEE Trans Circuits Syst I, Reg Papers 9:2042-2054
    • (2009) IEEE Trans Circuits Syst I, Reg Papers , vol.9 , pp. 2042-2054
    • Fu, B.1    Ampadu, P.2
  • 183
    • 0021660523 scopus 로고
    • Automatic-repeat-request error-control schemes
    • Lin S, Costello D, Miller M (1984) Automatic-repeat-request error-control schemes. IEEE Commun Mag 12:5-17
    • (1984) IEEE Commun Mag , vol.12 , pp. 5-17
    • Lin, S.1    Costello, D.2    Miller, M.3
  • 184
    • 0029779792 scopus 로고    scopus 로고
    • Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview
    • Srinivasan RG (1996) Modeling the cosmic-ray-induced soft-error rate in integrated circuits: an overview. IBM J Res Dev 1:77-89
    • (1996) IBM J Res Dev , vol.1 , pp. 77-89
    • Srinivasan, R.G.1
  • 187
    • 24144461667 scopus 로고    scopus 로고
    • Performance evaluation and design trade-offs for network-on-chip interconnect architectures
    • Pande PP, Grecu C, Ivanov A, Saleh R (2005) Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans Comput 54:1025-1040
    • (2005) IEEE Trans Comput , vol.54 , pp. 1025-1040
    • Pande, P.P.1    Grecu, C.2    Ivanov, A.3    Saleh, R.4
  • 189
    • 85008053864 scopus 로고    scopus 로고
    • An 80-tile sub-100-W teraFLOPS processor in 65-nm CMOS
    • Vangal S et al (2008) An 80-tile sub-100-W teraFLOPS processor in 65-nm CMOS. IEEE J Solid-State Circuits 43:29-41
    • (2008) IEEE J Solid-state Circuits , vol.43 , pp. 29-41
    • Vangal, S.1
  • 191
    • 0026852964 scopus 로고
    • High speed parallel CRC circuits in VLSI
    • Pei BT, Zukowski C (1992) High speed parallel CRC circuits in VLSI. IEEE Trans Commun 40:653-657
    • (1992) IEEE Trans Commun , vol.40 , pp. 653-657
    • Pei, B.T.1    Zukowski, C.2
  • 192
    • 77953346386 scopus 로고    scopus 로고
    • Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects
    • Fu B, Ampadu P (2010) Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects. IET Comput Digit Tech 4:251-261
    • (2010) IET Comput Digit Tech , vol.4 , pp. 251-261
    • Fu, B.1    Ampadu, P.2
  • 195
    • 34547345637 scopus 로고    scopus 로고
    • Design of on-chip error correction systems for multilevel NOR and NAND flash memories
    • Sun F, Devarajan S, Rose K, Zhang T (2007) Design of on-chip error correction systems for multilevel NOR and NAND flash memories. IET Circuits Devices Syst 1:241-249
    • (2007) IET Circuits Devices Syst , vol.1 , pp. 241-249
    • Sun, F.1    Devarajan, S.2    Rose, K.3    Zhang, T.4
  • 200
    • 40949110161 scopus 로고    scopus 로고
    • Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding
    • Special Issue on Defect and Fault Tolerance
    • Ganguly A, Pande PP, Belzer B, Grecu C (2008) Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding. J Electron Testing Theory Appl (JETTA), 67-81, Special Issue on Defect and Fault Tolerance
    • (2008) J Electron Testing Theory Appl (JETTA) , pp. 67-81
    • Ganguly, A.1    Pande, P.P.2    Belzer, B.3    Grecu, C.4
  • 201
    • 70350622990 scopus 로고    scopus 로고
    • Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects
    • Ganguly A, Pande PP, Belzer B (2009) Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects. IEEE Trans Very Large Scale Integr (VLSI) Syst 17:1626-1639
    • (2009) IEEE Trans Very Large Scale Integr (VLSI) Syst , vol.17 , pp. 1626-1639
    • Ganguly, A.1    Pande, P.P.2    Belzer, B.3
  • 202
    • 34248590882 scopus 로고    scopus 로고
    • Coding for reliable on-chip buses: A class of fundamental bounds and practical codes
    • Sridhara S, Shanbhag RN (2007) Coding for reliable on-chip buses: a class of fundamental bounds and practical codes. IEEE Trans Comput-Aided Des Integr Circuits Syst 5:977-982
    • (2007) IEEE Trans Comput-aided des Integr Circuits Syst , vol.5 , pp. 977-982
    • Sridhara, S.1    Shanbhag, R.N.2
  • 206
    • 27944447304 scopus 로고    scopus 로고
    • Coding for reliable on-chip buses: Fundamental limits and practical codes
    • Sridhara R S, Shanbhag RN(2005) Coding for reliable on-chip buses: Fundamental limits and practical codes. In: Proceedings VLSI design, pp 417-422
    • (2005) Proceedings VLSI Design , pp. 417-422
    • Sridhara, R.S.1    Shanbhag, R.N.2
  • 208
    • 0034795679 scopus 로고    scopus 로고
    • Two schemes to reduce interconnect delay in bi-directional and unidirectional buses
    • Nose K, Sakurai T (2001) Two schemes to reduce interconnect delay in bi-directional and unidirectional buses. In: Proceedings of VLSI symposium, pp 193-194
    • (2001) Proceedings of VLSI Symposium , pp. 193-194
    • Nose, K.1    Sakurai, T.2
  • 209
    • 77952709993 scopus 로고    scopus 로고
    • Exploiting parity computation latency for on-chip crosstalk reduction
    • Fu B, Ampadu P (2010) Exploiting parity computation latency for on-chip crosstalk reduction. IEEE Trans Circuits Syst II: Express Briefs 57:399-403
    • (2010) IEEE Trans Circuits Syst II: Express Briefs , vol.57 , pp. 399-403
    • Fu, B.1    Ampadu, P.2
  • 211
    • 50549092307 scopus 로고    scopus 로고
    • Reducing interconnect delay uncertainty via hybrid polarity repeater insertion
    • Akl CJ, Bayoumi MA (2008) Reducing interconnect delay uncertainty via hybrid polarity repeater insertion. IEEE Trans Very Large Scale Integr (VLSI) Syst 16:1230-1239
    • (2008) IEEE Trans Very Large Scale Integr (VLSI) Syst , vol.16 , pp. 1230-1239
    • Akl, C.J.1    Bayoumi, M.A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.