Effects of interconnect process variations on signal integrity

2006 IEEE International Systems-on-Chip Conference, SOC

Volumn , Issue , 2006, Pages 281-284

  Demircan, Ertugrul ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; ELECTRIC RESISTANCE; PARAMETER ESTIMATION; SIGNAL ANALYSIS; VLSI CIRCUITS;

INTERCONNECT PARASITICS; INTERCONNECT PROCESS VARIATIONS; RESPONSE SURFACE MODEL (RSM);

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 43749110041     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2006.283898     Document Type: Conference Paper

References (9)