A systematic approach for parallel CRC computations

Journal of Information Science and Engineering

Volumn 17, Issue 3, 2001, Pages 445-461

  Shieh, M D ^a   Sheu, M H ^a   Chen, C H ^a   Lo, H F ^a  

^a NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

Author keywords

Error control code; Galois field; Linear feedback shift register (LFSR); Parallel cyclic redundancy code (CRC) computation; VLSI design

Indexed keywords

DATA HANDLING; DATA STORAGE EQUIPMENT; HARDWARE; PARALLEL PROCESSING SYSTEMS; SHIFT REGISTERS; TELECOMMUNICATION SYSTEMS; VLSI CIRCUITS;

CYCIC REDUNDANCY CODES (CRC);

CODES (SYMBOLS);

EID: 0035329161     PISSN: 10162364     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (14)

1. A tutorial on CRC computations
2. Cyclic code redundancy
3. Byte-wise CRC calculation
4. Parallel CRC lets many lines use one circuit
5. Parallel CRC generation
6. Fast CRC calculation
7. High-speed parallel CRC circuits in VLSI
8. A high-performance CMOS 32-bit parallel CRC engine
9. New efficient designs for XOR and XNOR functions on the transistor level