Buffer insertion for noise and delay optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 11, 1999, Pages 1633-1645

  Alpert, Charles J ^a   Devgan, Anirudh ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; OPTIMIZATION; SPURIOUS SIGNAL NOISE; TREES (MATHEMATICS);

BUFFER INSERTION; STEINER TREE;

BUFFER CIRCUITS;

EID: 0033350807     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.806808     Document Type: Article

References (32)

1. C. J. Alpert and A. Devgan, "Wire segmenting for improved buffer insertion," in Proc. 34th IEEE/ACM Design Automation Conf., 1997, pp. 588-593.
2. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
3. C. L. Berman, J. L. Carter, and K. F. Day, "The fanout problem: From theory to practice," in Advanced Research in VLSI: Proc. 1989 Decennial Caltech Conference, C. L. Seitz, Ed. Cambridge, MA; MIT Press, Mar. 1989, pp. 69-99.
4. I. Catt, "Crosstalk (noise) in digital systems," IEEE Trans. Electron. Comput., vol. ED-16, pp. 743-763, 1967.
5. C. C. N. Chu and D. F. Wong, "Closed form solution to simultaneous buffer insertion/sizing and wire sizing," in Proc. Int. Symp. Physical Design, 1997, pp. 192-197.
6. -, "A new approach to simultaneous buffer insertion and wire sizing," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1997, pp. 614-621.
7. J. Cong, L. He, C.-K. Koh, and P. H. Madden, "Performance optimization of VLSI interconnect layout," Integration: The VLSI J., vol. 21, pp. 1-94, 1996.
8. A. Devgan, "Efficient coupled noise estimation for on-chip interconnects," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1997, pp. 147-151.
9. S. Dhar and M. A. Franklin, "Optimum buffer circuits for driving long uniform lines," IEEE J. Solid-State Circuits, vol. 26, pp. 32-410, Jan 1991.
10. W. C. Elmore, "The transient response of damped linear network with particular regard to wideband amplifiers," J. Appl. Phys., vol. 19, pp. 55-63, 1948.
11. P. Feldmann and R. W. Fruend, "Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm," in Proc. ACM/IEEE Design Automation Conf., 1995, pp. 474-479.
12. L. Gal, "On-chip crosstalk-The new signal integrity challenge," in Proc. Custom Integrated Circuits Conf., 1995, pp. 12.1.1-12.1.4.
13. M. Z.-W. Kang, W. W.-M. Dai, T. Dillinger, and D. P. LaPotin, "Delay bounded buffered tree construction for timing driven floorplanning," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1997, pp. 707-712.
14. L. N. Kannan, P. R. Suaris, and H.-G. Fang, "A methodology and algorithms for post-placement delay optimization," in Proc. 31st IEEE/ACM Design Automation Conf., 1994, pp. 327-332.
15. R. Kay and L. Pileggi, "PRIMO: Probability interpretation of moments for delay calculation," in Proc. ACM/IEEE Design Automation Conf., 1998, pp. 463-468.
16. D. Kirkpatrick and A. Sangiovanni-Vincentelli, "Techniques for crosstalk avoidance in design of high-performance digital systems," in Proc. IEEE Int. Conf. Computer-Aided Design, 1994, pp. 616-619.
17. J. Lillis, "Timing optimization for multi-source nets: Characterization and optimal repeater insertion," in Proc. 34th IEEE/ACM Design Automation Conf., 1997, pp. 214-219.
18. J. Lillis, C.-K. Cheng, and T.-T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE J. Solid-State Circuits, vol. 31, pp. 437-447, Mar. 1996.
19. _, "Simultaneous routing and buffer insertion for high-performance interconnect," in Proc. 6th Great Lakes Symp. Physical Design, 1996, pp. 7-12.
20. S. Lin and M. Marek-Sadowska, "A fast and efficient algorithm for determining fanout trees in large networks," in Proc. European Conf. Design Automation, 1991, pp. 539-544.
21. T. Lin, E. Acar, and L. Pileggi, "h-gamma: An RC delay metric based on a gamma distribution approximation of the homogeneous response," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1998, pp. 19-25.
22. L. W. Nagel, "SPICE2, a computer program to simulate semiconductor circuits," Univ. California, Berkeley, CA, Tech. Rep. ERL-M520, May 1975.
23. T. Okamoto and J. Cong, "Interconnect layout optimization by simultaneous Steiner tree construction and buffer insertion," in Proc. 5th ACM/S1GDA Physical Design Workshop, 1996, pp. 1-6.
24. P. Penfield and J. Rubinstein, "Signal delay in RC tree networks," in Proc. ACM/IEEE Design Automation Conf., 1981, pp. 613-617.
25. L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Compute r-Aided Design, vol. 9, pp. 352-366, Apr. 1990.
26. J. Rahmeh, "The 3d-noise user guide," IBM, Austin, TX, Internal Rep., 1997.
27. C. Ratzlaff and L. T. Pillage, "RICE: Rapid interconnect circuit evaluator using asymptotic waveform evaluation," IEEE Trans. ComputerAided Design, vol. 13, pp. 763-776, June 1994.
28. K. Shephard and V. Narayan, "Noise in submicron digital design," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1996, pp. 524-531.
29. T. Stohr, M. Alt, A. Hetzel, and J. Koehl, "Analysis, reduction and avoidance of crosstalk on VLSI chips," in Proc. Int. Symp. Physical Design, 1998, pp. 211-218.
30. R. R Tummala and E. J. Ryamszewski, Microelectronics Packaging Handbook. New York: Van Nostrand, Reinhold, 1989.
31. L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. Int. Symp. Circuits and Systems, 1990, pp. 865-868.
32. A. Vittal and M. Marek-Sadowska, "Crosstalk reduction for VLSI," IEEE Trans. Computer-Aided Design, vol. 16, pp. 290-298, Mar. 1997.