Characterization of soft errors caused by single event upsets in CMOS processes

IEEE Transactions on Dependable and Secure Computing

Volumn 1, Issue 2, 2004, Pages 128-143

  Karnik, Tanay ^a   Hazucha, Peter ^a   Patel, Jagdish ^b  

^a INTEL CORPORATION   (United States)

^b NASA HEADQUARTERS   (United States)

Author keywords

Error tolerance; High performance; Reliability; Single event upset; Soft error

Indexed keywords

CODES (SYMBOLS); COSMIC RAYS; ELECTRIC FIELDS; ERROR CORRECTION; NETWORKS (CIRCUITS); NEUTRON BEAMS; RANDOM ACCESS STORAGE; RELIABILITY; VLSI CIRCUITS;

ERROR TOLERANCE; HIGH PERFORMANCE; SINGLE EVENT UPSETS; SOFT ERRORS;

CMOS INTEGRATED CIRCUITS;

EID: 9144234352     PISSN: 15455971     EISSN: None     Source Type: Journal    
DOI: 10.1109/TDSC.2004.14     Document Type: Article

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