Managing on-chip inductive effects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 6, 2002, Pages 789-798

  Massoud, Yehia ^a   Majors, Steve ^b   Kawa, Jamil ^a   Bustami, Tareq ^c   MacMillen, Don ^a   White, Jacob ^d  

^a SYNOPSYS INC   (United States)

^b Mindspeed Technologies   (United States)

^c MOTOROLA INC   (United States)

^d Massachusetts Institute of Technology   (United States)

Author keywords

Crosstalk noise; Delay; Differential signaling; Inductance; Inductive effects; Interdigitated technique

Indexed keywords

CROSSTALK; ELECTRIC RESISTANCE; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE;

CROSSTALK NOISE;

INDUCTANCE;

EID: 0037004834     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.807763     Document Type: Article

References (32)

1. D. Priore, "Inductance on silicon for sub-micron CMOS VLSI," in Proc. Symposium on VLSI Circuits, 1993.
2. K. Shepard and V. Narayanan, "Noise in deep submicron digital design," in Proc. International Conference on Computer Aided Design, Nov. 1996.
3. H. Smith, A. Deutsch, S. Mehrotra, D. Widiger, M. Bowen, A. Dansky, G. Kopcsay, and B. Krauter, "R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chip," Proc. IEEE Custom Integrated Circuits Conference, July 2001.
4. A. Deutsch, H. Smith, G. Kopcsay, C. Surovic, B. Krauter, and P. Coteus, "Multi-line crosstalk and common-mode noise analysis," Proc. IEEE Custom Integrated Circuits Conference, pp. 317-319, July 2000.
5. A. Deutsch, P. Coteus, G. Kopcsay, H. Smith, C. Surovic, B. Krauter, D. Edelstein, and P. Restle, "On-chip wiring challenges for gigahertz operation," Proc. IEEE, vol. 89, pp. 529-555, Apr. 2001.
6. Y. Massoud and J. White, "Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit cross-talk," IEEE Trans. VLSI Syst., to be published.
7. K. Gala, D. Blaauw, J. Wang, V. Zolotov, and M. Zhao, "Inductance 101: Analysis and design issues," in Proc. Design Automation Conference, June 2001.
8. Y. Ismail and E. Friedman, "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," IEEE Trans. VLSI Syst., vol. 8, pp. 195-206, Apr. 2000.
9. B. Krauter, S. Mehrotra, and V. Chandramouli, "Including inductive effects in interconnect timing analysis," Proc. IEEE Conference on Electrical Performance of Electronic Packaging, pp. 445-451, May 1999.
10. A. Deutsch, G. Kopcsay, P. Restle, H. Smith, G. Katopis, W. Becker, P. Coteus, C. Surovic, B. Rubin, R. Dunne, T. Gallo, K. Jenkins, L. Terman, R. Dennard, G. Sai-Halasz, B. Krauter, and D. Knebel, "When are transmission-line effects important for on-chip interconnections?," IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836-1846, Oct. 1997.
11. L. Pileggi, "Coping with RC(L) interconnect design headaches," in Proc. International Conference on Computer Aided Design, Nov. 1995.
12. S. Khatri, A. Mehrotra, R. Brayton, A. Sangiovanni-Vincentelli, and R. Otten, "A novel VLSI layout fabric for deep sub micron applications," in Proc. Design Automation Conference, June 1999.
13. C. Alpert, A. Devgan, and S. Quay, "Buffer insertion for noise and delay optimization," in Proc. Design Automation Conference, June 1998.
14. T. Xue, E. Kuh, and Y. Qingjian, "A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies," Proc. IEEE Multi-Chip Module Conference, pp. 117-122, 1996.
15. K. Chaudhary, A. Onozawa, and E. Kuh, "A spacing algorithm for performance enhancement and cross-talk reduction," in Proc. International Conference on Computer Aided Design, Nov. 1993.
16. J. Cong, L. He, C.-K. Koh, and Z. Pan, "Interconnect sizing and spacing with consideration of coupling capacitance," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 1164-1169, Sept. 2001.
17. T. Xue, E. Kuh, and D. Wang, "Post global routing crosstalk synthesis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 16, pp. 1418-1430, Dec. 1997.
18. T. Gao and C. Liu, "Minimum crosstalk channel routing," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, pp. 465-474, May 1996.
19. K. Lepak, I. Luwandi, and L. He, "Simultaneous shield insertion and net ordering under explicit RLC noise constraint," in Proc. Design Automation Conference, 2001, pp. 199-202.
20. G. Zhong, C. Koh, and K. Roy, "A twisted-bundle layout structure for minimizing inductive coupling noise," in Proc. International Conference on Computer Aided Design, Nov. 2000.
21. B. Gieseke, R. Allmon, D. Bailey, B. Benschneider, S. Britton, J. Clouser, H. Fair, J. Farrell, M. Gowan, C. Houghton, J. Keller, T. Lee, D. Leibholz, S. Lowell, M. Matson, R. Matthew, V. Peng, M. Quinn, D. Priore, M. Smith, and K. Wilcox, "A 600 MHz superscalar RISC microprocessor with out-of-order execution," Proc. IEEE International Solid-State Circuits Conference, Feb. 1997.
22. D. Bailey and B. Benschneider, "Clocking design and analysis for a 600-mhz alpha microprocessor," IEEE J. Solid-State Circuits, vol. 33, pp. 1627-1633, November 1998.
23. L. Vakanas, S. Hasan, A. Cangellaris, and J. Prince, "Effects of floating planes in three-dimensional packaging structures on simultaneous switching noise," IEEE Trans. Compon., Packag., Manufact. Technol., Part B: Adv. Packag., vol. 21, pp. 434-440, November 1998.
24. K. Nabors and J. White, "Fast capacitance extraction of general three-dimensional structures," IEEE Trans. Microwave Theory Tech., vol. 40, June 1992.
25. M. Kamon, M. Tsuk, and J. White, "Fasthenry: A mutipole-accelerated 3-D inductance extraction program," IEEE Trans. Microwave Theory Tech., vol. 42, pp. 1750-1758, Sept. 1994.
26. R. Harrington, Field Computations by Moment Methods. New York: MacMillan, 1968.
27. L. Greengard, The Rapid Evaluation of Potential Fields in Particle Systems. Cambridge, MA: M.I.T. Press, 1988.
28. Hspice: Avanti Corporation, 2000.
29. H. Zhang, V. George, and J. Rabaey, "Low-swing on-chip signaling techniques: Effectiveness and robustness," IEEE Trans. VLSI Syst., vol. 8, pp. 264-272, June 2000.
30. H. Shin and D. Hodges, "A 250-Mbits CMOS crosspoint switch," IEEE J. Solid State Circuits, vol. 24, Apr. 1989.
31. P. Brennan, N. Raver, and A. E. Ruehli, "Three dimensional inductance computations with partial element equivalent circuits," IBM J. Res. Dev., pp. 661-668, Nov. 1979.
32. A. E. Ruehli, "Inductance calculations in a complex integrated circuit enviornment," IBM J. Res. Dev., pp. 470-481, Sept. 1972.