On-chip interconnection architecture of the tile processor

IEEE Micro

Volumn 27, Issue 5, 2007, Pages 15-31

  Wentzlaff, David ^a   Griffin, Patrick ^a   Hoffmann, Henry ^a   Bao, Liewei ^a   Edwards, Bruce ^a   Ramey, Carl ^a   Mattina, Matthew ^a   Miao, Chyi Chang ^a   Brown III, John F ^a   Agarwal, Anant ^a  

^a Tilera Corp   (United States)

Author keywords

Mesh networks; MIMD processors; Multicore architectures; On chip interconnection; On chip interconnection networks; Parallel architectures; Parallel processing; Tile processors

Indexed keywords

COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS;

INTERCONNECTION LIBRARY; MULTICORE PROCESSOR; ON-CHIP INTERCONNECTION NETWORKS; TILE PROCESSOR;

INTERCONNECTION NETWORKS;

EID: 36849030305     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2007.4378780     Document Type: Article

References (5)

1. M.B. Taylor et al., "Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams," Proc. Int'l Symp. Computer Architecture (ISCA 04), IEEE CS Press, 2004, pp. 2-13.
2. E. Waingold et al., "Baring It All to Software: Raw Machines," Computer, vol. 30, no. 9, Sept. 1997, pp. 86-93.
3. M.B. Taylor et al., "Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures," Proc. Int'l Symp. High-Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 341-353.
4. MPI: A Message-Passing Interface Standard, Message Passing Interface Forum, 1994; http://www.mpi-forum.org/docs/mpi-11-html/ mpi-report.html.
5. J.M. Lebak. Polymorphous Computing Architectures (PCA) Example Application 4: Corner-Turn, tech. report, MIT Lincoln Laboratory, 2001.