-
2
-
-
0029369234
-
Modeling andcharacterization of long on-chip interconnections for high-performance microprocessors
-
Sept
-
A. Deutsch, G. V. Kopcsay,C.W. Surovic, B. J. Rubin, L. M. Terman, R. P.Dunne and T. Gallo, "Modeling andCharacterization of Long On-chip Interconnections for High-Performance Microprocessors", final report, ARPA HSCD Contract C-556003, September 1995. Also appeared in IBM Journal of Research and Development 39(5), Sept. 1995, pp. 547-567.
-
(1995)
Final Report, ARPA HSCD Contract C-556003, September 1995. Also Appeared in IBM Journal of Research and Development
, vol.39
, Issue.5
, pp. 547-567
-
-
Deutsch, A.1
Kopcsay, G.V.2
Surovic, C.W.3
Rubin, B.J.4
Terman, L.M.5
Dunne, R.P.6
Gallo, T.7
-
3
-
-
0031333822
-
Clock cycle estimations for futuremicroprocessor generations
-
Austin, October
-
P. D. Fisher, "Clock Cycle Estimations for FutureMicroprocessor Generations", Proc. IEEE Innovative Systems in Silicon, Austin, October 1997.
-
(1997)
Proc. IEEE Innovative Systems in Silicon
-
-
Fisher, P.D.1
-
5
-
-
0030672523
-
Physical designchallenges for performance
-
April
-
D. P. LaPotin, U. Ghoshal,E.Chiprout andS. R. Nassif, "Physical DesignChallenges for Performance", International Symposiumon Physical Design, April 1997, pp. 225-226.
-
(1997)
International Symposiumon Physical Design
, pp. 225-226
-
-
Lapotin, D.P.1
Ghoshal, U.2
Chiprout, E.3
Nassif, S.R.4
-
6
-
-
84893790745
-
GigaScale integration: Is the sky the limit?
-
Hot Chips IX, Stanford, CA, August 25-26
-
J. Meindl, "GigaScale Integration: Is the Sky the Limit?", keynote presentation slides, Hot Chips IX, Stanford, CA, August 25-26, 1997.
-
(1997)
Keynote Presentation Slides
-
-
Meindl, J.1
-
7
-
-
0030645043
-
A roadmap of cad tool changes for sub-micron interconnect problems
-
April
-
L. Scheffer, "A Roadmap of CAD Tool Changes for Sub-micron Interconnect Problems", International Symposium on Physical Design, April 1997, pp. 104-109.
-
(1997)
International Symposium on Physical Design
, pp. 104-109
-
-
Scheffer, L.1
-
9
-
-
0030686706
-
Analysis and justification of a simple, practical 2 1/2-d capacitance extraction methodology
-
June
-
J. Cong, L.He,A. B.Kahng,D.Noice,N. Shirali and S.H.-C.Yen, "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", Proc. Design Automation Conference, June 1997.
-
(1997)
Proc. Design Automation Conference
-
-
Cong, J.1
He, L.2
Kahng, A.B.3
Noice, D.4
Shirali, N.5
Yen, S.H.-C.6
-
10
-
-
84889183331
-
IC vendors prepare for 0.25-micron leap
-
September 16
-
L. Gwennap, "IC Vendors Prepare for 0.25-Micron Leap", Microprocessor Report, September 16, 1996, pp. 11-15.
-
(1996)
Microprocessor Report
, pp. 11-15
-
-
Gwennap, L.1
-
12
-
-
84889187074
-
Interconnectmodeling and design in high-speedVLSI/ULSI systems
-
October
-
S.-Y. Oh,K.-J. Chang,N. Chang andK. Lee, "Interconnectmodeling and design in high-speedVLSI/ULSI systems", Proc. International Conference on Computer Design: VLSI in Computers and Processors,October 1992, pp. 184-189.
-
(1992)
Proc. International Conference on Computer Design: VLSI in Computers and Processors
, pp. 184-189
-
-
Oh, S.-Y.1
Chang, K.-J.2
Chang, N.3
Lee, K.4
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