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Volumn , Issue , 1998, Pages 471-478

Interconnect tuning strategies for high-performance ICs

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT TECHNOLOGY; GLOBAL INTERCONNECTS; INTERCONNECT PERFORMANCE; MANUFACTURABILITY; OPTIMUM TECHNIQUE; REPEATER INSERTION; SIGNAL DISTRIBUTION; SIGNAL PERFORMANCE;

EID: 84893765568     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655900     Document Type: Conference Paper
Times cited : (78)

References (12)
  • 3
    • 0031333822 scopus 로고    scopus 로고
    • Clock cycle estimations for futuremicroprocessor generations
    • Austin, October
    • P. D. Fisher, "Clock Cycle Estimations for FutureMicroprocessor Generations", Proc. IEEE Innovative Systems in Silicon, Austin, October 1997.
    • (1997) Proc. IEEE Innovative Systems in Silicon
    • Fisher, P.D.1
  • 6
    • 84893790745 scopus 로고    scopus 로고
    • GigaScale integration: Is the sky the limit?
    • Hot Chips IX, Stanford, CA, August 25-26
    • J. Meindl, "GigaScale Integration: Is the Sky the Limit?", keynote presentation slides, Hot Chips IX, Stanford, CA, August 25-26, 1997.
    • (1997) Keynote Presentation Slides
    • Meindl, J.1
  • 7
    • 0030645043 scopus 로고    scopus 로고
    • A roadmap of cad tool changes for sub-micron interconnect problems
    • April
    • L. Scheffer, "A Roadmap of CAD Tool Changes for Sub-micron Interconnect Problems", International Symposium on Physical Design, April 1997, pp. 104-109.
    • (1997) International Symposium on Physical Design , pp. 104-109
    • Scheffer, L.1
  • 10
    • 84889183331 scopus 로고    scopus 로고
    • IC vendors prepare for 0.25-micron leap
    • September 16
    • L. Gwennap, "IC Vendors Prepare for 0.25-Micron Leap", Microprocessor Report, September 16, 1996, pp. 11-15.
    • (1996) Microprocessor Report , pp. 11-15
    • Gwennap, L.1
  • 11


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.