메뉴 건너뛰기




Volumn 51, Issue 12, 2004, Pages 2417-2435

Performance optimization of critical nets through active shielding

Author keywords

Capacitive coupling; Inductive coupling; On chip interconnects; Shields

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC SHIELDING; ELECTRIC WIRE; MATHEMATICAL MODELS; MOS DEVICES; OPTIMIZATION;

EID: 10944228725     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.838247     Document Type: Article
Times cited : (31)

References (28)
  • 1
    • 0031645246 scopus 로고    scopus 로고
    • "Interconnect scaling: Signal integrity and performance in future high-speed CMOS designs"
    • D. Sylvester et al., "Interconnect scaling: signal integrity and performance in future high-speed CMOS designs," in Symp. on VLSI TechnologyDig. Tech. Papers, 1998, pp. 42-43.
    • (1998) Symp. on VLSI Technology Dig. Tech. Papers , pp. 42-43
    • Sylvester, D.1
  • 2
    • 33646922057 scopus 로고    scopus 로고
    • "The future of wires"
    • R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires," Proc. IEEE, vol. 89, pp. 490-504, 2001.
    • (2001) Proc. IEEE , vol.89 , pp. 490-504
    • Ho, R.1    Mai, K.W.2    Horowitz, M.A.3
  • 3
    • 0036292725 scopus 로고    scopus 로고
    • "Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance"
    • M. H. Chowdhury et al., "Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance," in Proc. Int Symp. Circuits and Systems (ISCAS), 2002, pp. 197-200.
    • (2002) Proc. Int Symp. Circuits and Systems (ISCAS) , pp. 197-200
    • Chowdhury, M.H.1
  • 4
    • 0033724256 scopus 로고    scopus 로고
    • "Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization"
    • L. He and K. M. Lepak, "Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization," in Proc. Int. Symp. Physical Design (ISPD), 2000, pp. 55-60.
    • (2000) Proc. Int. Symp. Physical Design (ISPD) , pp. 55-60
    • He, L.1    Lepak, K.M.2
  • 6
    • 0032678594 scopus 로고    scopus 로고
    • "A novel VLSI layout fabric for deep sub-micron applications"
    • S. Khatri et al., "A novel VLSI layout fabric for deep sub-micron applications," in Proc. Design Automation Conf. (DAC , 1999, pp. 491-496.
    • (1999) Proc. Design Automation Conf. (DAC) , pp. 491-496
    • Khatri, S.1
  • 9
    • 0031623454 scopus 로고    scopus 로고
    • "Layout techniques for minimizing on-chip interconnect self inductance"
    • Y. Massoud et al., "Layout techniques for minimizing on-chip interconnect self inductance," in Proc. Design Automation Conf. (DAC), 1998, pp. 566-571.
    • (1998) Proc. Design Automation Conf. (DAC) , pp. 566-571
    • Massoud, Y.1
  • 10
    • 84893639086 scopus 로고    scopus 로고
    • "Reduction of interconnect delay by exploiting cross-talk"
    • S. van Dijk and D. Hély, "Reduction of interconnect delay by exploiting cross-talk," in Proc. Eur. Solid State Circuits Conf., 2001, pp. 316-319.
    • (2001) Proc. Eur. Solid State Circuits Conf. , pp. 316-319
    • van Dijk, S.1    Hély, D.2
  • 11
    • 0042769408 scopus 로고    scopus 로고
    • "Designing fast on-chip interconnects for deep submicrometer technologies"
    • R. Hossain, F. Viglione, and M. Cavalli, "Designing fast on-chip interconnects for deep submicrometer technologies," IEEE Trans. VLSI Syst., vol. 11, pp. 276-280, 2003.
    • (2003) IEEE Trans. VLSI Syst. , vol.11 , pp. 276-280
    • Hossain, R.1    Viglione, F.2    Cavalli, M.3
  • 12
    • 0034841994 scopus 로고    scopus 로고
    • "Modeling and analysis of differential signaling for minimizing inductive cross-talk"
    • Y. Massoud et al., "Modeling and analysis of differential signaling for minimizing inductive cross-talk," in Proc. Design Automation Conf. (DAC), 2001, pp. 804-809.
    • (2001) Proc. Design Automation Conf. (DAC) , pp. 804-809
    • Massoud, Y.1
  • 13
    • 10944254327 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors. ITRS. [Online]. Available
    • International Technology Roadmap for Semiconductors. (2000) ITRS. [Online]. Available: http://public.itrs.net
    • (2000)
  • 14
    • 0028498583 scopus 로고    scopus 로고
    • "FastHenry: A multipole-accelerated 3-D inductance extraction program"
    • Sept
    • M. Kamon, M. Tsuk, and J. White, "FastHenry: A multipole-accelerated 3-D inductance extraction program," IEEE Trans. Microwave Theory Tech., vol. 42, pp. 1750-1758, Sept. 1999.
    • (1999) IEEE Trans. Microwave Theory Tech. , vol.42 , pp. 1750-1758
    • Kamon, M.1    Tsuk, M.2    White, J.3
  • 15
    • 10944262077 scopus 로고    scopus 로고
    • Synopsys, Inc., [Online], Available
    • Synopsys, Inc. (2002). [Online] Available: http://www.synopsys.com/ products/avmrg/raphael.̈html
    • (2002)
  • 16
    • 10944245884 scopus 로고    scopus 로고
    • Synopsys, Inc., [Online], Available
    • Synopsys, Inc. (2002). [Online] Available: http://www.synopsys.com/ products/avmrg/hspice.̈html
    • (2002)
  • 17
    • 0035439983 scopus 로고    scopus 로고
    • "Interconnect sizing and spacing with consideration of coupling capacitance"
    • J. Cong et al., "Interconnect sizing and spacing with consideration of coupling capacitance," IEEE Trans. Computer-Aided Design, vol. 20, pp. 1164-1169, 2001.
    • (2001) IEEE Trans. Computer-Aided Design , vol.20 , pp. 1164-1169
    • Cong, J.1
  • 18
    • 0025594311 scopus 로고
    • "Buffer placement in distributed RC-tree networks for minimal Elmore delay"
    • L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay," in Proc. Int. Symp. Circuits and Systems, vol. 2, 1990, pp. 865-868.
    • (1990) Proc. Int. Symp. Circuits and Systems , vol.2 , pp. 865-868
    • van Ginneken, L.P.P.P.1
  • 20
    • 0032072770 scopus 로고    scopus 로고
    • "Repeater design to reduce delay and power in resistive interconnect"
    • May
    • V. Adler and E. Friedman, "Repeater design to reduce delay and power in resistive interconnect," IEEE Trans. Circuits Syst. II, vol. 45, pp. 607-616, May 1998.
    • (1998) IEEE Trans. Circuits Syst. II , vol.45 , pp. 607-616
    • Adler, V.1    Friedman, E.2
  • 21
    • 0035327739 scopus 로고    scopus 로고
    • "Repeater insertion in tree structured inductive interconnect"
    • May
    • Y. Ismail and E. Friedman, "Repeater insertion in tree structured inductive interconnect," IEEE Trans. Circuits Syst. II, vol. 48, pp. 471-481, May 2001.
    • (2001) IEEE Trans. Circuits Syst. II , vol.48 , pp. 471-481
    • Ismail, Y.1    Friedman, E.2
  • 23
    • 10944246227 scopus 로고    scopus 로고
    • "An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7-1.4 V"
    • S. Thompson et al., "An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7-1.4 V," in Proc. Int. Electron Devices Meeting (IEDM), 2001, pp. 11.6.1-11.6.4.
    • (2001) Proc. Int. Electron Devices Meeting (IEDM)
    • Thompson, S.1
  • 24
    • 0030141612 scopus 로고    scopus 로고
    • "Performance computation for precharacterized CMOS gates with RC loads"
    • May
    • F. Dartu, N. Menezes, and L. T. Pileggi, "Performance computation for precharacterized CMOS gates with RC loads," IEEE Trans. Computer-Aided Design, vol. 15, pp. 544-553, May 1996.
    • (1996) IEEE Trans. Computer-Aided Design , vol.15 , pp. 544-553
    • Dartu, F.1    Menezes, N.2    Pileggi, L.T.3
  • 25
    • 0031704625 scopus 로고    scopus 로고
    • "New efficient algorithms for computing effective capacitance"
    • Apr
    • A. B. Kahng and S. Muddu, "New efficient algorithms for computing effective capacitance," in Proc. Int. Symp. Physical Design, Apr. 1998, pp. 147-151.
    • (1998) Proc. Int. Symp. Physical Design , pp. 147-151
    • Kahng, A.B.1    Muddu, S.2
  • 27
    • 0035334849 scopus 로고    scopus 로고
    • "A clock distribution network for microprocessors"
    • May
    • P. Restle et al., "A clock distribution network for microprocessors," IEEE J. Solid-State Circuits, vol. 36, pp. 792-799, May 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , pp. 792-799
    • Restle, P.1
  • 28
    • 10944262078 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors. ITRS. [Online]. Available
    • International Technology Roadmap for Semiconductors. (2001) ITRS. [Online]. Available: http://public.itrs.net
    • (2001)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.