Two schemes to reduce interconnect delay in bi-directional and uni-directional buses

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 193-194

  Nose, K ^a   Sakurai, T ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COUPLED CIRCUITS;

COUPLING CAPACITANCE;

VLSI CIRCUITS;

EID: 0034795679     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of sub-quarter micron ULSI
2. Regenerative feedback repeaters for programmable interconnects