RLC signal integrity analysis of high-speed global interconnects

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2000, Pages 731-733

  Huang, X ^a   Cao, Y ^a   Sylvester, D ^a   Lin, S ^a   King, T J ^a   Hu, C ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COUPLED CIRCUITS; LARGE SCALE SYSTEMS; SPURIOUS SIGNAL NOISE;

CHEMICAL MECHANICAL POLISHING (CMP);

MICROPROCESSOR CHIPS;

EID: 0034453548     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Quick on-chip self and mutual-inductance screen
2. Return-limited inductances: A practical approach to on-chip inductance extraction
3. A novel vlsi layout fabric for deep submicron applications