Reducing bus delay in submicron technology using coding

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 109-114

  Sotiriadis, P P ^a   Chandrakasan, A ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Couplings; Delay effects; Delay estimation; Differential equations; Encoding; Laplace equations; Noise figure; Parasitic capacitance; Voltage; Wire

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; COUPLINGS; DIFFERENTIAL EQUATIONS; ELECTRIC POTENTIAL; ENCODING (SYMBOLS); LAPLACE EQUATION; MULTIPROCESSING SYSTEMS; NOISE FIGURE;

CAPACITIVE COUPLINGS; DELAY EFFECTS; DELAY ESTIMATION; DISTRIBUTED MODELING; INDEPENDENT SOURCES; PARASITIC CAPACITANCE; SUBMICRON TECHNOLOGIES; TRANSMISSION OF DATA;

WIRE;

EID: 84949766294     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913289     Document Type: Conference Paper

References (11)

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