Low power and fault tolerant encoding methods for on-chip data transfer in practical applications

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E88-A, Issue 12, 2005, Pages 3282-3288

  Komatsu, Satoshi ^a,b,c   Fujita, Masahiro ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b IEEE   (Japan)

^c IPSJ   (Japan)

Author keywords

Bus encoding; ECC EDC; Low power; Reliability

Indexed keywords

DATA TRANSFER; ENCODING (SYMBOLS); ENERGY UTILIZATION; MICROPROCESSOR CHIPS; OPTIMIZATION; RELIABILITY; SIGNAL PROCESSING; VLSI CIRCUITS;

BUS ENCODING; ECC/EDC; LOW POWER; SIGNAL TRANSITIONS;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 29144534264     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e88-a.12.3282     Document Type: Article

References (13)

1. R. Hamming, "Error detecting and error correcting codes," Bell Syst. Tech. J., vol.29, pp. 147-160, 1950.
2. M.R. Stan and W.P. Burleson, "Bus-invert coding for low power I/O," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.3, no. 1, pp.49-58, March 1995.
3. L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano, "Asymptotic zero-transition activity encoding for address buses in low-power microprocessor-based systems," IEEE 7th Great Lakes Symposium on VLSI, pp.77-82, March 1997.
4. L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano, "Address bus encoding techniques for system-level power optimization," Design Automation and Test in Europe, pp.861-866, 1998.
5. L. Benini, A. Macii, E. Macii, M. Poncino, and R. Scarsi, "Synthesis of low-overhead interfaces for power-efficient communication over wide buses," Design Automation Conference '99, pp.128-133, June 1999.
6. P. Sotiriadis, A. Wang, and A. Chandrakasan, "Transition pattern coding: An approach to reduce energy in interconnect," 26th European Solid-State Circuit Conference, pp.320-323, Sept. 2000.
7. S. Ramprasada, N.R. Shanbhag, and I.N. Hajj, "A coding framework for low-power address and data busses," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.7, no.2, pp.212-221, 1999.
8. D. Bertozzi, L. Benini, and G.D. Micheli, "Low power error resilient encoding for on-chip data buses," Design Automation and Test in Europe 2002, pp.102-109, 2002.
9. S.R. Sridhara and N.R. Shanbhag, "Coding for system-on-chip networks: A unified framework," Design Automation Conference 2004, pp. 103-106, 2004.
10. T.V. Ramabadran, "A coding scheme for m-out-of-n codes," IEEE Trans. Commun., vol.38, no.8, pp.1156-1163, Aug. 1990.
11. J.M. Berger, "A note on error detecting codes for asymmetric channels," Inf. Control, vol.4, pp.68-73, March 1961.
12. http://www.simplescalar.com/
13. R. Hegde and N.R. Shanbhag, "Toward achieving energy efficiency in presence of deep submicron noise," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.8, no.4, pp.379-391, Aug. 2000.