A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 1, 2011, Pages 173-183

  Howard, Jason ^a   Dighe, Saurabh ^a   Vangal, Sriram R ^a   Ruhl, Gregory ^a   Borkar, Nitin ^a   Jain, Shailendra ^b   Erraguntla, Vasantha ^b   Konow, Michael ^c   Riepen, Michael ^c   Gries, Matthias ^c   Droege, Guido ^c   Lund Larsen, Tor ^c   Steibl, Sebastian ^c   Borkar, Shekhar ^a   De, Vivek K ^a   Van Der Wijngaart, Rob ^a  

^a INTEL CORPORATION   (United States)

^b INTEL TECHNOLOGY INDIA PVT LTD   (India)

^c INTEL DEUTSCHLAND GMBH   (Germany)

Author keywords

2D routing; CMOS digital integrated circuits; DDR3 controllers; dynamic voltage frequency scaling (DVFS); IA 32; message passing; network on chip (NoC)

Indexed keywords

2D-ROUTING; CMOS DIGITAL INTEGRATED CIRCUITS; DDR3 CONTROLLERS; DYNAMIC VOLTAGE FREQUENCY SCALING (DVFS); IA-32; NETWORK ON CHIP;

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; CONTROLLERS; DIES; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ENERGY MANAGEMENT; INTEGRATED CIRCUITS; MESSAGE PASSING; MICROPROCESSOR CHIPS; SERVERS; VLSI CIRCUITS; VOLTAGE REGULATORS;

ROUTERS;

EID: 78650922410     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2079450     Document Type: Conference Paper

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