Exploiting parity computation latency for on-chip crosstalk reduction

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 57, Issue 5, 2010, Pages 399-403

  Fu, Bo ^a   Ampadu, Paul ^a  

^a University of Rochester   (United States)

Author keywords

Crosstalk avoidance; Error control coding (ECC); On chip interconnects; Reliability; Skewed transition

Indexed keywords

COMPUTATION THEORY; COMPUTER CIRCUITS; ENERGY UTILIZATION; ERRORS; RELIABILITY;

CAPACITIVE COUPLINGS; CROSSTALK AVOIDANCE; DELAY UNCERTAINTIES; ERROR CONTROL CODING; ERROR PROBABILITIES; ON-CHIP CROSSTALK; ON-CHIP INTERCONNECTS; SKEWED TRANSITION;

CROSSTALK;

EID: 77952709993     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2010.2043472     Document Type: Article

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