Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 767-770

  Mehrotra, Vikas ^a   Nassif, Sani ^a   Boning, Duane ^a   Chung, James ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS;

HIGH-SPEED MICROPROCESSOR INTERCONNECTS; MANUFACTURING VARIATION;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0032272981     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)