Scaling analysis of multilevel interconnect temperatures for high-performance ICs

IEEE Transactions on Electron Devices

Volumn 52, Issue 12, 2005, Pages 2710-2719

  Im, Sungjun ^a   Srivastava, Navin ^b   Banerjee, Kaustav ^b   Goodson, Kenneth E ^a  

^a Stanford University   (United States)

^b University of California   (United States)

Author keywords

Electrothermal analysis; Interconnects; Joule heating; Low dielectrics; Metal resistivity; Size effect; Temperature scaling; Very large scale integrated system (VLSI); Via effect

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER SIMULATION; COPPER; ELECTRIC CONDUCTIVITY; FINITE ELEMENT METHOD; HEAT RESISTANCE; INTEGRATED CIRCUIT TESTING; PERMITTIVITY; THERMAL CONDUCTIVITY; THERMOANALYSIS; VLSI CIRCUITS;

ELECTROTHERMAL ANALYSIS; HIGH-PERFORMANCE INTEGRATED CIRCUITS; INTERLAYER DIELECTRICS; METAL RESISTIVITY; MULTILEVEL INTERCONNECT TEMPERATURES; SCALING ANALYSIS; SIZE EFFECT; TEMPERATURE SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 29244444803     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.859612     Document Type: Article

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