Coding for reliable on-chip buses: Fundamental limits and practical codes

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 417-422

  Sridhara, Srinivasa R ^a   Shanbhag, Naresh R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK AVOIDANCE; LOW-SWING SIGNALING; ON-CHIP BUSES;

CMOS INTEGRATED CIRCUITS; CROSSTALK; ERROR CORRECTION; MICROPROCESSOR CHIPS; RELIABILITY;

ENCODING (SYMBOLS);

EID: 27944447304     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, pp. 663-670, June 1994.
2. D. Sylvester and C. Hu, "Analytical modeling and characterization of deep-submicrometer interconnect," Proc. IEEE, vol. 89, pp. 634-664, May 2001.
3. H. Zhang, V. George, and J. Rabaey, "Low-swing on-chip signaling techniques: effectiveness and robustness," IEEE Trans. VLSI Syst., vol. 8, pp. 264-272, June 2000.
4. J. Yim and C. Kung, "Reducing cross-coupling among interconnect wires in deep-submicron datapath design," in Proc. DAC, 1999, pp. 485-490.
5. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "A coding framework for low-power address and data busses," IEEE Trans. VLSI Syst., vol. 7, pp. 212-221, June 1999.
6. M. R. Stan and W. P. Burleson, "Bus-invert coding for low-power I/O," IEEE Trans. VLSI Syst., vol. 3, pp. 49-58, Mar. 1995.
7. K. Kim, K. Baek, N. Shanbhag, C. Liu, and S. Kang, "Coupling-driven signal encoding scheme for low-power interface design," in Proc. ICCAD, 2000, pp. 318-321.
8. Y. Zhang, J. Lach, K. Skadron, and M. R. Stan, "Odd/even bus invert with two-phase transfer for buses with coupling," in Proc. ISLPED, 2002, pp. 80-83.
9. P. P. Sotiriadis, "Interconnect modeling and optimization in deep sub-micron technologies," Ph.D. dissertation, Massachusetts Institute of Technology, Cambridge, May 2002.
10. C. Duan, A. Tirumala, and S. P. Khatri, "Analysis and avoidance of cross-talk in on-chip buses," in Proc. Hot Interconnects, 2001, pp. 133-138.
11. B. Victor and K. Keutzer, "Bus encoding to prevent crosstalk delay," in Proc. ICCAD, 2001, pp. 57-63.
12. S. R. Sridhara, A. Ahmed, and N. R. Shanbhag, "Area and energy-efficient crosstalk avoidance codes for on-chip buses," in Proc. ICCD, 2004.
13. D. Bertozzi, L. Benini, and G. D. Micheli, "Low power error resilient encoding for n-chip data buses," in Proc. DATE, 2002, pp. 102-109.
14. R. Hegde and N. R. Shanbhag, "Toward achieving energy efficiency in the presence of deep submicron noise," IEEE Trans. VLSI Syst., vol. 8, pp. 379-391, Aug. 2000.
15. F. J. MacWilliams and N. J. A. Sloane, The Theory of Error-Correcting Codes. New York, NY: North-Holland, 1977.
16. S. R. Sridhara and N. R. Shanbhag, "Coding for system-on-chip networks: a unified framework," in Proc. DAC, 2004, pp. 103-106.
17. K. Patel and I. Markov, "Error-correction and crosstalk avoidance in DSM busses," in Proc. SLIP, 2003, pp. 9-14.
18. S. R. Sridhara and N. R. Shanbhag, "Coding for reliable on-chip buses: fundamental limits and practical codes," in preparation.