Adaptive error control for nanometer scale network-on-chip links

IET Computers and Digital Techniques

Volumn 3, Issue 6, 2009, Pages 643-659

  Yu, Q ^a   Ampadu, P ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ERROR; ADAPTIVE ERROR CONTROL; AREA OVERHEAD; AVERAGE ENERGY; AVERAGE THROUGHPUT; CONFIGURABLE; DETECTION METHODS; ENERGY REDUCTION; ERROR CONTROL; ERROR DETECTION AND CORRECTION; ERROR DETECTION CODE; ERROR RATE; HIGH NOISE ENVIRONMENTS; HYBRID AUTOMATIC REPEAT REQUEST; MESSAGE TRANSMISSIONS; NANOMETER-SCALE NETWORKS; NANOSCALE NETWORKS; RETRANSMISSION POLICIES; RUNTIMES; SIMULATION RESULT; THREE ORDERS OF MAGNITUDE;

ADAPTIVE CONTROL SYSTEMS; CODES (SYMBOLS); ELECTRIC NETWORK TOPOLOGY; ERROR CORRECTION; NANOTECHNOLOGY; SWITCHING CIRCUITS;

ERROR DETECTION;

EID: 70350721965     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2008.0132     Document Type: Article

References (35)

1. Ho, R., Mai, K.W., and Horowitz, M.A.: ' The future of wires ', Proc. IEEE, 2001, 89, (4), p. 490-504 10.1109/5.920580 0018-9219
2. Constantinescu, C.: ' Trends and challenges in VLSI circuit reliability ', IEEE Micro., 2003, 23, (4), p. 14-19 10.1109/MM.2003.1225959 0272-1732
3. Salminen E., Kulmala A., Hämäläinen T.D.: 'Survey of network-on-chip proposals'. White paper, OCP-IP, March 2008, p. 13
4. Dally, W.J., and Towles, B.: ' Route packets, not wires: on-chip interconnection networks ', Proc. 38th Design Automation Conf. (DAC'01), Las Vegas, NV, USA, June, 2001, p. 684-689
5. Benini, L., and Micheli, G.D.: ' Networks on chips: a new SoC paradigm ', Computer, 2002, 35, (1), p. 70-78 10.1109/2.976921 0018-9162 (Pubitemid 34069383)
6. Bjerregaard, T., and Mahadevan, S.: ' A survey of research and practices of network-on-chip ', ACM Comput. Surv., 2006, 38, (1), p. 1-51 0360-0300
7. Dumitraş, T., Kerner, S., and Mǎrculescu, R.: ' Towards on-chip fault-tolerant communication ', Proc. Asia and South Pacific Design Automation Conf., Kitakyushu, Japan, January, 2003, p. 225-232
8. Mǎrculescu, R.: ' Networks-on-chip: the quest for on-chip fault-tolerant communication ', Proc. IEEE Computer Society Ann. Symp. VLSI (ISVLSI'03), Tampa, FL, USA, February, 2003, p. 8-12
9. Bertozzi, D., Benini, L., and Micheli, G.D.: ' Low power error resilient encoding for on-chip data buses ', Proc. Design, Automation, and Test in Europe (DATE'02), Le Palais des Congres, Paris, France, March, 2002, p. 102-109
10. Murali, S., Benini, L., Irwin, M.J., and Micheli, G.D.: ' Analysis of error recovery schemes for networks on chips ', IEEE Design Test Comput., 2005, 22, (5), p. 434-442
11. Ali, M., Welzl, M., Hessler, S., and Hellebrand, S.: ' A fault tolerant mechanism for handling permanent and transient failures in a network on chip ', Proc. Intl. Technology: New Generations (ITNG'07), Las Vegas, NV, USA, April, 2007, p. 1027-1032
12. Bertozzi, D., Benini, L., and Micheli, G.D.: ' Error control scheme for on-chip communication links: the energy-reliability tradeoff ', IEEE Trans. Comput. Aided Design Integr. Circuits Syst., 2005, 24, (6), p. 818-831 10.1109/TCAD.2005.847907 (Pubitemid 40818746)
13. Komatsu, S., and Fujita, M.: ' Low power and fault tolerant encoding methods for on-chip data transfer in practical applications ', IEICE Trans. Fundam., 2005, E88-A, (12), p. 3282-3289
14. Sridhara, S.R., and Shanbhag, N.R.: ' Coding for system-on-chip networks: a unified framework ', IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2006, 13, p. 655-667 10.1109/TVLSI.2005.848816 1063-8210
15. Ejlali, A., Al-Hashimi, B.M., Rosinger, P., and Miremadi, S.G.: ' Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks ', Proc. Design, Automation, and Test in Europe (DATE'07), Acropolis, Nice, France, April, 2007, p. 1647-1652
16. Sridhara, S.R., and Shanbhag, N.R.: ' Coding for reliable on-chip buses: a class of fundamental bounds and practical codes ', IEEE Trans. Comput. Aided Design Integr. Circuits Syst., 2007, 26, (5), p. 977-982 10.1109/TCAD.2006. 884418 (Pubitemid 46748281)
17. Li, L., Vijaykrishnan, N., Kandemir, M., and Irwin, M.J.: ' Adaptive error protection for energy efficiency ', Proc. Intl. Conf. Computer Aided Design (ICCAD'03), San Jose, CA, USA, November, 2003, p. 2-7
18. Palit, A.K., Duganapallia, K.K., and Anheiera, W.: ' Crosstalk fault modeling in defective pair of interconnects ', Integr. VLSI J., 2008, 41, (1), p. 27-37 0167-9260
19. Ganguly, A., Pande, P.P., Belzer, B., and Grecu, C.: ' Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding ', J. Electron. Test., 2008, 24, (1), p. 67-81
20. Micheli, G.D., and Benini, L.: ' Networks on chips ', (Morgan Kaufmann, 2007)
21. Zimmer, H., and Jantsch, A.: ' A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip ', Proc. Intl. Conf. Hardware/Software Codesign and Syst. Synthesis (CODES-ISSS'03), Newport Beach, CA, USA, October, 2003, p. 188-193
22. Rossi, D., Angelini, P., and Metra, C.: ' Configurable error control scheme for NoC signal integrity ', Proc. IEEE Intl. On-Line Testing Symp. (IOLTS 2007), Hersonissos-Heraklion, July, 2007, Crete, Greece, p. 43-48
23. Lehtonen, T., Liljeberg, P., and Plosila, J.: ' Online reconfigurable self-timed links for fault tolerant NoC ', VLSI Des., 2007, p. 13
24. Yu, Q., and Ampadu, P.: ' Configurable error correction for multi-wire errors in switch-to-switch links ', Proc. IEEE Intl. SOC Conf. (SOCC'08), Newport Beach, CA, USA, September, 2008, p. 71-74
25. Worm, F., Ienne, P., Thiran, P., and Micheli, G.D.: ' A robust self-calibrating transmission scheme for on-chip network ', IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2005, 13, (1), p. 126-139 1063-8210
26. Yu, Q., and Ampadu, P.: ' Adaptive error control for reliable systems-on-chip ', Proc. Intl. Symp. Circuits and Syst. (ISCAS'08), Seattle, WA, USA, May, 2008, p. 832-835
27. Yu, Q., and Ampadu, P.: ' Adaptive error control for NoC switch-to-switch links in a variable noise environment ', Proc. 23rd IEEE Intl. Symp. Defect and Fault Tolerance in VLSI System (DFT'08), Cambridge, MA, USA, October, 2008, p. 352-360
28. Lin, S., and Costello, D.J.: ' Error control coding ', 2nd (Prentice-Hall, 1983), 2004
29. Nunez-Yanez, J.L., Edwards, D., and Coppola, A.M.: ' Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems ', IET Comput. Dig. Tech., 2008, 2, (3), p. 184-198
30. Kousa, M., and Turner, L.: ' Reliability-throughput optimization for adaptive forward error correction systems ', IEE Proc. Commun., 1996, 143, (6), p. 341-346 1350-2425
31. Minn, H., Zeng, M., and Bhargava, V.K.: ' On ARQ scheme with adaptive error control ', IEEE Trans. Veh. Technol., 2001, 50, (6), p. 1426-1436 0018-9545
32. Fu, B., and Ampadu, P.: ' A dual-mode hybrid ARQ scheme for energy efficiency on-chip interconnects ', Proc. 3rd Intl. Conf. Nano-Networks (Nano-Net'08), Boston, MA, USA, September, 2008, p. 5
33. http://www.eas.asu.edu/~ptm/, accessed March 2009
34. Bertozzi, D., and Benini, L.: ' Xpipe: a network-on-chip architecture for gigascale systems-on-chip ', IEEE Circuit Syst. Mag., 2004, 4, p. 18-31
35. H.264/AVC JM Reference, http://iphome.hhi.de/suehring/tml/, accessed March 2009